High capacity and automatic functional extraction tool for industrial VLSI circuit designs

In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV-Extract and is part of a comprehensive Formal Equivalence Verification (FEV) system developed at Intel to verify modern microprocessor designs. FEV-Extract employs a powerful hierarchical analysis procedure, and advanced and generic algorithms for automatic recognition of logical primitives, to cope with variety of circuit design styles and their complexity. Logic equations are then extracted to generate a behavioral RTL model described in industrial standard HDL languages, to be used in the formal equivalence verification, logic simulation, synthesis and testability flows.

[1]  Gadi Singer,et al.  NETHDL: abstraction of schematics to high-level HDL , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[2]  A. Greiner,et al.  YAGLE, a second generation functional abstractor for CMOS VLSI circuits , 1998, Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186).

[3]  Timothy Kam,et al.  State machine abstraction from circuit layouts using BDDs: applications in verification and synthesis , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[4]  Carl-Johan H. Seger,et al.  CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination , 2001, CAV.

[5]  Randal E. Bryant.  Extraction of gate level models from transistor circuits by four-valued symbolic analysis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[6]  Timothy Kam,et al.  Comparing layouts with HDL models: a formal verification technique , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[7]  Randal E. Bryant,et al.  Algorithmic Aspects of Symbolic Switch Network Analysis , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Zurab Khasidashvili,et al.  An enhanced cut-points algorithm in formal equivalence verification , 2001, Sixth IEEE International High-Level Design Validation and Test Workshop.

[9]  Randal E. Bryant,et al.  Boolean Analysis of MOS Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.