Cache Design for Low Leakage Power Based on Way-Decay Cache

The power dissipation of cache on chip is the main part of entire processor chip dissipation, so this paper proposed a new WDC(Way-Decay Cache). This novel cache architecture can turn off some unused ways and run in configuration with low power, otherwise it runs in normal configuration, so it can reduce the average leakage power. Compared with the current cache architecture for low power, this architecture with resizable ways and low leakage power has the characteristic of fewer additional logics, simpler implementation and better hardware implementation. The experiments show the architecture can decrease energy consumption without significantly hindering performance.