Retargetable generation of code selectors from HDL processor models

Besides high code quality, a primary issue in embedded code generation is retargetability of code generators. This paper presents techniques for automatic generation of code selectors from externally specified processor models. In contrast to previous work, our retargetable compiler RECORD does not require tool-specific modelling formalisms, but starts from general HDL processor models. From an HDL model, all processor aspects needed for code generation are automatically derived. As demonstrated by experimental results, short turnaround times for retargeting are achieved, which permits study of the HW/SW trade-off between processor architectures and program execution speed.

[1]  Peter Marwedel,et al.  Verification of Hardware Descriptions by Retargetable Code Generation , 1989, 26th ACM/IEEE Design Automation Conference.

[2]  Roderic Geoffrey Galton Cattell,et al.  Formalization and Automatic Derivation of Code Generators , 1982 .

[3]  T. C. May,et al.  Instruction-set matching and selection for DSP and ASIP code generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[4]  A. Knoll,et al.  Translating Signal Flowcharts into Microcode for Custom Digital Signal Processors , 1993 .

[5]  Chuck Monahan,et al.  Symbolic Modeling and Evaluation of Data Paths , 1995, 32nd Design Automation Conference.

[6]  B. Wess Automatic instruction code generation based on trellis diagrams , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[7]  Clifford Liem,et al.  Trends In Embedded Systems Technology , 1996 .

[8]  Andrew S. Tanenbaum,et al.  Structured Computer Organization , 1976 .

[9]  Hugo De Man,et al.  A graph based processor model for retargetable code generation , 1996, Proceedings ED&TC European Design and Test Conference.

[10]  Robert Steven Glanville,et al.  A Machine Independent Algorithm for Code Generation and Its Use in Retargetable Compilers , 1977 .

[11]  Rainer Leupers,et al.  A BDD-based frontend for retargetable compilers , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[12]  Marco Platzner,et al.  Hardware-Software Codesign , 1997, IEEE Des. Test Comput..

[13]  J. Praet,et al.  Programmable Chips in Consumer Electronics and Telecommunications Architectures and Design Technology , 1996 .

[14]  Sharad Malik,et al.  Optimal code generation for embedded memory non-homogeneous register architectures , 1995 .

[15]  Dhananjay M. Dhamdhere,et al.  Efficient Retargetable Code Generation Using Bottom-up Tree Pattern Matching , 1990, Comput. Lang..

[16]  Jochen A. G. Jess,et al.  Efficient code generation for in-house DSP-cores , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[17]  G. Goossens,et al.  PROGRAMMABLE CHIPS IN CONSUMER ELECTRONICS AND TELECOMMUNICATIONS , 1996 .

[18]  Andrew S. Tanenbaum,et al.  Structured computer organization, 3rd Edition , 1990 .

[19]  Gert Goossens,et al.  Code Generation for Embedded Processors , 1995 .

[20]  M. Morris Mano,et al.  Computer system architecture , 1982 .

[21]  Christopher W. Fraser,et al.  Engineering a simple, efficient code-generator generator , 1992, LOPL.

[22]  Rainer Leupers,et al.  Time-constrained code compaction for DSPs , 1995 .