105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

Abstract We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO 2 /TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances ( I ON , I OFF , transconductance, low field mobility, S , DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties ( μ h  ∼ 250 cm 2 /V/s, I ON  = 436 μA/μm for L G  = 105 nm), and OFF current densities comparable or better than those reported in the literature.

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