Designing robust checkers in the presence of massive timing errors
暂无分享,去创建一个
[1] Giovanni De Micheli,et al. A robust self-calibrating transmission scheme for on-chip networks , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[2] Paolo Ienne,et al. Soft self-synchronising codes for self-calibrating communication , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[3] Cameron McNairy,et al. Itanium 2 Processor Microarchitecture , 2003, IEEE Micro.
[4] Jay M. Berger. A Note on Error Detection Codes for Asymmetric Channels , 1961, Inf. Control..
[5] Charles V. Freiman. Optimal Error Detection Codes for Completely Asymmetric Binary Channels , 1962, Inf. Control..
[6] Michael Nicolaidis. Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).
[7] Michael Nicolaidis,et al. Carry checking/parity prediction adders and ALUs , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[8] Cecilia Metra,et al. Exploiting ECC redundancy to minimize crosstalk impact , 2005, IEEE Design & Test of Computers.
[9] David Blaauw,et al. Making typical silicon matter with Razor , 2004, Computer.
[10] Kaushik Roy,et al. Self calibrating circuit design for variation tolerant VLSI systems , 2005, 11th IEEE International On-Line Testing Symposium.
[11] Dhiraj K. Pradhan,et al. IEEE International On-Line Testing Symposium , 2008 .
[12] Bella Bose. On Unordered Codes , 1991, IEEE Trans. Computers.
[13] David L. Dill,et al. Efficient self-timing with level-encoded 2-phase dual-rail (LEDR) , 1991 .