Peak power estimation using genetic spot optimization for large VLSI circuits

Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP) of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.

[1]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[2]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[3]  Kurt Keutzer,et al.  Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Kurt Keutzer,et al.  Estimation of average switching activity in combinational and sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[5]  Ibrahim N. Hajj,et al.  Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits , 1993, 30th ACM/IEEE Design Automation Conference.

[6]  Farid N. Najm,et al.  A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Harish Kriplani,et al.  Worst case voltage drops in power and ground buses of CMOS VLSI circuits , 1994 .

[8]  Farid N. Najm,et al.  Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuitsy , 1995, 32nd Design Automation Conference.

[9]  Enrico Macii,et al.  Computing the Maximum Power Cycles of a Sequential Circuit , 1995, 32nd Design Automation Conference.

[10]  Sung-Mo Kang,et al.  Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits , 1995, ICCAD.

[11]  Michael S. Hsiao,et al.  Automatic test generation using genetically-engineered distinguishing sequences , 1996, Proceedings of 14th VLSI Test Symposium.

[12]  Kaushik Roy,et al.  Maximum power estimation for sequential circuits using a test generation based technique , 1996, Proceedings of Custom Integrated Circuits Conference.

[13]  Kaushik Roy,et al.  Accurate power estimation of CMOS sequential circuits , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Michael S. Hsiao,et al.  Effects of delay models on peak power estimation of VLSI sequential circuits , 1997, ICCAD 1997.

[15]  Salvador Manich,et al.  Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[16]  Michael S. Hsiao,et al.  Sequential circuit test generation using dynamic state traversal , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[17]  Kaushik Roy,et al.  COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits , 1997, ICCAD 1997.

[18]  Michael S. Hsiao,et al.  K2: an estimator for peak sustainable power of VLSI circuits , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[19]  K. Roy,et al.  Power sensitivity—a new method to estimate power dissipation considering uncertain specifications of primary inputs , 1997, ICCAD 1997.