An Integrated Cache Timing and Power Model

1 CACTI CACTI [6] calculates access and cycle times of hardware caches. It uses an analytical model to estimate delay down both tag and data paths to determine the best configuration for a given cache size, block size, and associativity (at 0:80 m technology size). Figure 1 demonstrates the architecture of the cache in the analytical model. In addition to providing timing data for each portion of the data and tag paths, CACTI also returns the number of data and tag arrays (in terms of the number of word line and bit line divisions), and the number of sets mapped to a single wordline, for both tag and data arrays. CACTI does not model cache area, but does estimate wire resistance and capacitance based on cache configuration.