Don't cares in synthesis: theoretical pitfalls and practical solutions
暂无分享,去创建一个
[1] Michel R. C. M. Berkelaar,et al. Efficient orthonormality testing for synthesis with pass-transistor selectors , 1995, ICCAD.
[2] Wayne H. Wolf,et al. Performance-driven synthesis in controller-datapath systems , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[3] M. Berkelaar,et al. Efficient orthonormality testing for synthesis with pass-transistor selectors , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[4] Andreas Kuehlmann,et al. Control optimization in high-level synthesis using behavioral don't cares , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[5] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[6] Leon Stok,et al. High-level synthesis in an industrial environment , 1995, IBM J. Res. Dev..
[7] Daniel Brand,et al. In the driver's seat of BooleDozer , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[8] Leendert M. Huisman,et al. A small test generator for large designs , 1992, Proceedings International Test Conference 1992.
[9] Srinivas Devadas,et al. Redundancies and don't cares in sequential logic synthesis , 1990, J. Electron. Test..
[10] Yahiko Kambayashi,et al. The Transduction Method-Design of Logic Networks Based on Permissible Functions , 1989, IEEE Trans. Computers.
[11] Premachandran R. Menon,et al. Multi-level Logic Optimization By Implication Analysis , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[12] Daniel Brand,et al. Incremental synthesis , 1994, ICCAD '94.
[13] Robert K. Brayton,et al. Multi-Level Synthesis For Safe Replaceability , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[14] Daniel Brand. Redundancy and Don't Cares in Logic Synthesis , 1983, IEEE Transactions on Computers.
[15] Robert K. Brayton,et al. Multi-Level Logic Simplification Using Don't Cares and Filters , 1989, 26th ACM/IEEE Design Automation Conference.
[16] Jing-Yang Jou,et al. BECOME: behavior level circuit synthesis based on structure mapping , 1988, DAC '88.
[17] Robert K. Brayton,et al. An exact minimizer for Boolean relations , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[18] Tiziano Villa,et al. NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.
[19] Robert K. Brayton,et al. Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] Daniel Brand,et al. Timing Analysis Using Functional Analysis , 1988, IEEE Trans. Computers.
[21] Robert K. Brayton,et al. MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[22] Hiroshi Sawada,et al. A new method to express functional permissibilities for LUT based FPGAs and its applications , 1996, ICCAD 1996.
[23] Alberto L. Sangiovanni-Vincentelli,et al. MUSTANG: state assignment of finite state machines targeting multilevel logic implementations , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[24] Robert K. Brayton,et al. Integrating functional and temporal domains in logic design , 1991 .
[25] David Hung-Chang Du,et al. Circuit enhancement by eliminating long false paths , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.