A Self-Reconfigurable Implementation of the JPEG Encoder

Dynamic reconfiguration allows to selectively substitute blocks of logic at run-time in order to improve the area efficiency of a FPGA design. This paper presents the design of a JPEG Encoder which exploits this feature. We propose a mixed HW/SW architecture, where most compute-intensive components of the application are mapped to application-specific HW cores. These cores dynamically alternate on the FPGA. Our purpose is to describe a real-world application of reconfigurable computing, illustrating how this approach allows for saving area with negligible performance overhead. We built a fully-working prototype, which demonstrates that the reconfigurable JPEG encoder achieves 29.6% area saving, 1.5% performance loss, and negligible power overhead with respect to a solution which uses statically mapped HW cores.

[1]  Scott Hauck,et al.  The Chimaera reconfigurable functional unit , 1997, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Gianluca Palermo,et al.  A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[3]  Jürgen Becker,et al.  New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[4]  Idaku Ishii,et al.  Development of higher order autocorrelation vision chip , 2005, 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems.

[5]  Masatoshi Ishikawa,et al.  Device and System Development of General Purpose Digital Vision Chip , 2000, J. Robotics Mechatronics.

[6]  Tobias Becker,et al.  Modular partial reconfigurable in Virtex FPGAs , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[7]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[8]  Jeff Mason,et al.  Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[9]  Misha Mahowald,et al.  A silicon model of early visual processing , 1993, Neural Networks.

[10]  Masatoshi Ishikawa,et al.  Vision chip architecture using general-purpose processing elements for 1 ms vision system , 1997, Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97.

[11]  Jürgen Becker,et al.  Methods for run-time failure recognition and recovery in dynamic and partial reconfigurable systems based on Xilinx Virtex-II Pro FPGAs , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[12]  Takio Kurita,et al.  A New Scheme for Practical Flexible and Intelligent Vision Systems , 1988, MVA.

[13]  Stamatis Vassiliadis,et al.  The MOLEN polymorphic processor , 2004, IEEE Transactions on Computers.

[14]  Ranga Vemuri,et al.  Rapid prototyping of reconfigurable coprocessors , 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

[15]  Nikil D. Dutt,et al.  Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Idaku Ishii,et al.  A digital vision chip specialized for high-speed target tracking , 2003 .

[17]  Sri Parameswaran,et al.  Heterogeneous multiprocessor implementations for JPEG:: a case study , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[18]  Tameesh Suri.  Improving instruction level parallelism through reconfigurable units in superscalar processors , 2007, CARN.

[19]  Francis Devos,et al.  A programmable artificial retina , 1993 .

[20]  Fabrizio Ferrandi,et al.  Caronte: a complete methodology for the implementation of partially dynamically self-reconfiguring systems on FPGA platforms , 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

[21]  Mark de Wit,et al.  A dynamic reconfiguration run-time system , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[22]  Masatoshi Ishikawa,et al.  Self-windowing for high speed vision , 1999, Proceedings 1999 IEEE International Conference on Robotics and Automation (Cat. No.99CH36288C).

[23]  Frank Vahid,et al.  The Softening of Hardware , 2003, Computer.

[24]  Jan-Erik Eklund,et al.  VLSI implementation of a focal plane image processor-a realization of the near-sensor image processing concept , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[25]  Masatoshi Ishikawa,et al.  Method of moment calculation for a digital vision chip system , 2000, Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception.