Voltage regulator based on an high-efficiency adaptive charge pump

In this paper, both a charge pump which changes its number of stages to achieve the minimum power consumption and a regulated voltage reference based on it is presented. The charge pump can modifies the number of stages from 1 to 3 through a proper assigning of the clock phases, and it uses the same amount of capacitance (i.e., silicon area) in all the topologies. The voltage regulator, based on the adaptive charge pump can dynamically select the equivalent stage behavior to maximize the power efficiency under power supply changes. The behavior of the circuits were confirmed through Eldo simulation using a 0.35 /spl mu/m CMOS EEPROM technology.

[1]  Michel Declercq,et al.  A high-efficiency CMOS voltage doubler , 1998, IEEE J. Solid State Circuits.

[2]  Gaetano Palumbo,et al.  Modeling and minimization of power consumption in charge pump circuits , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[3]  Kyeong-Sik Min,et al.  A fast pump-down V/sub BB/ generator for sub-1.5-V DRAMs , 2001 .

[4]  Toru Tanzawa,et al.  Optimization of word-line booster circuits for low-voltage flash memories , 1999 .

[5]  Chi-Chang Wang,et al.  Efficiency improvement in charge pump circuits , 1997 .

[6]  H. Morimura,et al.  A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's , 1998 .

[7]  E.C. Dijkmans,et al.  A -90 dB THD rail-to-rail input opamp using a new local charge pump in CMOS , 1997, Proceedings of the 23rd European Solid-State Circuits Conference.

[8]  G. Palumbo,et al.  Improved behavioral and design model of an Nth-order charge pump , 2000 .

[9]  Carla Golla,et al.  Flash Memories , 1999 .

[10]  Andrea Gerosa,et al.  A Sub-Micron CMOS Programmable Charge Pump for Implantable Pacemaker , 2001 .

[11]  H. Sato,et al.  A 126.6 mm/sup 2/ AND-type 512 Mb flash memory with 1.8 V power supply , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[12]  W. Weber,et al.  Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps , 2000, IEEE Journal of Solid-State Circuits.

[13]  Bram Nauta,et al.  Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology , 1998, IEEE J. Solid State Circuits.

[14]  T. Tanzawa,et al.  A dynamic analysis of the Dickson charge pump circuit , 1997, IEEE J. Solid State Circuits.

[15]  G. Palumbo,et al.  Design of an nth order Dickson voltage multiplier , 1996, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications.

[16]  Jieh-Tsorng Wu,et al.  MOS charge pumps for low-voltage operation , 1998, IEEE J. Solid State Circuits.