Solver technology for system-level to RTL equivalence checking

Checking the equivalence of a system-level model against an RTL design is a major challenge. The reason is that usually the system-level model is written by a system architect, whereas the RTL implementation is created by a hardware designer. This approach leads to two models that are significantly different. Checking the equivalence of real-life designs requires strong solver technology. The challenges can only be overcome with a combination of bit-level and word-level reasoning techniques, combined with the right orchestration. In this paper, we discuss solver technology that has shown to be effective on many real-life equivalence checking problems.

[1]  Cesare Tinelli,et al.  Solving SAT and SAT Modulo Theories: From an abstract Davis--Putnam--Logemann--Loveland procedure to DPLL(T) , 2006, JACM.

[2]  Werner Backes,et al.  A New Interval Approximation Supporting Bit Operations and Byte Access , 2006 .

[3]  Jerry R. Burch,et al.  Memory Modeling in ESL-RTL Equivalence Checking , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[4]  Joao Marques-Silva,et al.  GRASP-A new search algorithm for satisfiability , 1996, Proceedings of International Conference on Computer Aided Design.

[5]  Armin Biere,et al.  Effective Preprocessing in SAT Through Variable and Clause Elimination , 2005, SAT.

[6]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[7]  Carl Pixley,et al.  Constructing Efficient Formal Models from High-Level Descriptions Using Symbolic Simulation , 2005, International Journal of Parallel Programming.

[8]  David L. Dill,et al.  A Decision Procedure for Bit-Vectors and Arrays , 2007, CAV.

[9]  S.K. Srinivasan,et al.  Automatic Memory Reductions for RTL Model Verification , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[10]  Karem A. Sakallah,et al.  GRASP—a new search algorithm for satisfiability , 1996, ICCAD 1996.

[11]  Sergey Berezin,et al.  CVC Lite: A New Implementation of the Cooperating Validity Checker Category B , 2004, CAV.

[12]  Adnan Darwiche,et al.  A Lightweight Component Caching Scheme for Satisfiability Solvers , 2007, SAT.

[13]  Yuan Lu,et al.  Embedded tutorial: formal equivalence checking between system-level models and RTL , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..