Optimum Sizing and Compensation of Two-Stage CMOS Amplifiers Based On a Time-Domain Approach

This paper presents a new design methodology for optimum sizing and compensation of two-stage amplifiers based on a time-domain approach. This methodology allows the analysis of different topologies of amplifiers with an unlimited number of poles and zeros. The optimization process is performed by a software tool based on a genetic algorithm kernel integrated with open-source BSIM3v3 code. Using this tool together with the proposed design flow it is demonstrated, with consistent simulated results, that the optimum step-response is achieved using hybrid cascode-compensation comprising two un-equal sized capacitors.

[1]  Adolfo Steiger-Garção,et al.  Design methodology for optimization of analog building blocks using genetic algorithms , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[2]  Omid Shoaei,et al.  Hybrid cascode compensation for two-stage CMOS operational amplifiers , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[3]  Willy Sansen,et al.  Fast-settling CMOS two-stage operational transconductance amplifiers and their systematic design , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[4]  Georges Gielen,et al.  A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps , 1997, ICCAD 1997.

[5]  B.K. Ahuja,et al.  An improved frequency compensation technique for CMOS operational amplifiers , 1983, IEEE Journal of Solid-State Circuits.

[6]  R. Tavares,et al.  A general-purpose kernel based on genetic algorithms for optimization of complex analog circuits , 2001, Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257).