Towards power reduction through improved software design

As the use of computers has grown, so too has concern about the amount of power that they consume. Data centers, for example, are limited in scalability as they struggle with soaring energy costs as many large companies rely on fast, reliable, and round-the-clock computing services. On large-scale computing clusters, like data centers, even a small drop in power consumption can have large effects. Across computing contexts, reducing power consumed by computers has become a major focus. In this paper, we present a new approach and tool for mapping software design to power consumption and describe how such mappings can provide software designers and developers useful information about the power behavior of the software they are developing. The goal is for software engineers to use this information in designing and developing more energy efficient solutions.

[1]  Donatella Sciuto,et al.  Modeling assembly instruction timing in superscalar architectures , 2002, 15th International Symposium on System Synthesis, 2002..

[2]  Dipankar Sarma,et al.  Energy-aware task and interrupt management in Linux , 2009 .

[3]  Krste Asanovic,et al.  Reducing power density through activity migration , 2003, ISLPED '03.

[4]  J Kallinikos Green IT: Everything starts from the software , 2009 .

[5]  Daniel A. Jiménez,et al.  Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization , 2009, Trans. High Perform. Embed. Archit. Compil..

[6]  Mary Jane Irwin,et al.  Techniques for low energy software , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[7]  Jack W. Davidson,et al.  Memory access coalescing: a technique for eliminating redundant memory accesses , 1994, PLDI '94.

[8]  Diana Marculescu,et al.  Power aware microarchitecture resource scaling , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[9]  Y. N. Srikant,et al.  Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture , 2008, CF '08.

[10]  Donatella Sciuto,et al.  Energy estimation for 32-bit microprocessors , 2000, CODES '00.

[11]  Soheil Ghiasi,et al.  Efficient and scalable compiler-directed energy optimization for realtime applications , 2007 .

[12]  Carlo Brandolese,et al.  Source-Level Estimation of Energy Consumption and Execution Time of Embedded Software , 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

[13]  Ramon Canal,et al.  Design space exploration for multicore architectures: a power/performance/thermal view , 2006, ICS '06.

[14]  Mahmut T. Kandemir,et al.  The design and use of simplePower: a cycle-accurate energy estimation tool , 2000, Proceedings 37th Design Automation Conference.

[15]  Chi-Ying Tsui,et al.  Low Power Architectural Design and Compilation Techniques for High-Performance Processor , 1994 .

[16]  Mahmut T. Kandemir,et al.  DRAM energy management using software and hardware directed power mode control , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[17]  D. Sciuto,et al.  An instruction-level functionally-based energy estimation model for 32-bits microprocessors , 2000, DAC.

[18]  Trevor Mudge,et al.  Dynamic voltage scaling on a low-power microprocessor , 2001 .

[19]  Yung-Hsiang Lu,et al.  Automatic Run-Time Selection of Power Policies for Operating Systems , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[20]  Ulrich Kremer Low-Power/Energy Compiler Optimizations , 2004 .

[21]  Christopher W. Fraser,et al.  Engineering a simple, efficient code-generator generator , 1992, LOPL.

[22]  Daniel A. Jiménez,et al.  Efficient Program Power Behavior Characterization , 2007, HiPEAC.

[23]  Fred Douglis,et al.  Adaptive Disk Spin-Down Policies for Mobile Computers , 1995, Comput. Syst..

[24]  E. Musoll A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors , 2008, ISQED 2008.

[25]  Thomas D. Burd,et al.  Voltage scheduling in the IpARM microprocessor system , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[26]  Sharad Malik,et al.  Power analysis of embedded software: a first step towards software power minimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[27]  Amin Vahdat,et al.  ECOSystem: managing energy as a first class operating system resource , 2002, ASPLOS X.

[28]  Mahmut T. Kandemir,et al.  Energy-conscious compilation based on voltage scaling , 2002, LCTES/SCOPES '02.

[29]  Ulrich Kremer,et al.  The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction , 2003, PLDI '03.

[30]  Robin Kravets,et al.  Power management techniques for mobile communication , 1998, MobiCom '98.

[31]  Vincent K. N. Lau,et al.  Automatic Performance Setting for Dynamic Voltage Scaling , 2002, Wirel. Networks.

[32]  Mahmut T. Kandemir,et al.  Compiler-directed high-level energy estimation and optimization , 2005, TECS.