Analysis and optimization of power grids

As the complexity of power and ground networks increases, methods for efficient analysis and aggressive optimization of these networks become essential. Here, the authors describe efficient hierarchical methods for analyzing distribution networks. To optimize the networks, the authors call for techniques that reduce noise on the power grid, including topology selection, wire widening, and decoupling-capacitance insertion, combined with supply, signal, and clock network codesign.

[1]  Sani R. Nassif,et al.  Congestion-driven codesign of power and signal networks , 2002, DAC '02.

[2]  Hao Ji,et al.  How to efficiently capture on-chip inductance effects: introducing a new circuit element K , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[3]  Malgorzata Marek-Sadowska,et al.  Coping with buffer delay change due to power and ground noise , 2002, DAC '02.

[4]  Kaushik Roy,et al.  Decoupling capacitance allocation for power supply noise suppression , 2001, ISPD '01.

[5]  Andrew R. Conn,et al.  Noise considerations in circuit optimization , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Rajendran Panda,et al.  Hierarchical analysis of power distribution networks , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  James D. Z. Ma,et al.  Towards global routing with RLC crosstalk constraints , 2002, DAC '02.

[8]  David D. Ling,et al.  Power Supply Noise Analysis Methodology For Deep-submicron Vlsi Chip Design , 1997, Proceedings of the 34th Design Automation Conference.

[9]  Rob A. Rutenbar,et al.  Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs , 1996 .

[10]  Charlie Chung-Ping Chen,et al.  HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Sachin S. Sapatnekar,et al.  An algorithm for simulating power/ground networks using Pade approximants and its symbolic implementation , 1998 .

[12]  Sani R. Nassif,et al.  An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts , 2002, ISPD '02.

[13]  Resve A. Saleh,et al.  Clock skew verification in the presence of IR-drop in the powerdistribution network , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Jorge Nocedal,et al.  Algorithm 778: L-BFGS-B: Fortran subroutines for large-scale bound-constrained optimization , 1997, TOMS.

[15]  Ibrahim N. Hajj,et al.  Static timing analysis including power supply noise effect on propagation delay in VLSI circuits , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[16]  Sani R. Nassif,et al.  Multigrid-like technique for power grid analysis , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[17]  Sheldon X.-D. Tan,et al.  Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings , 1999, DAC '99.

[18]  Sachin S. Sapatnekar,et al.  Fast analysis and optimization of power/ground networks , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[19]  Lesley Polka,et al.  Package-Level Interconnect Design for Optimum Electrical Performance , 2000 .

[20]  S. Chowdhury.  Optimum Design of Reliable IC Power Networks Having General Graph Topologies , 1989, 26th ACM/IEEE Design Automation Conference.

[21]  Prashant Saxena,et al.  Shield count minimization in congested regions , 2002, ISPD '02.

[22]  Rajendran Panda,et al.  Design and analysis of power distribution networks in PowerPC microprocessors , 1998, DAC.

[23]  R. Rohrer.  The Generalized Adjoint Network and Network Sensitivities , 1969 .