论文信息 - A Block Cipher Circuit Design against Power Analysis

A Block Cipher Circuit Design against Power Analysis

In this paper, we will present a block cipher circuit design against Power Analysis. This design consists of usual masking and hiding method. For XOR, permutation and other linear layer, masking method of protection is used, but for S-box and other non-linear layer, hiding method is used in the reason that masking requires a lot of hardware consumption. We accomplished hardware implementation and Power Analysis in our research, whose test results proved that the design had strong capacity against Power Analysis. 200, 000 curves were extracted in our attack simulation, and the key successfully resisted complete recovery.

Zhimin Zhang | Zhigang Mao | Zheng Guo | Yuxiao Ling | Zeleng Zhuang

[1] Christophe Giraud,et al. An Implementation of DES and AES, Secure against Some Attacks , 2001, CHES.

[2] Hongying Liu,et al. Information Hiding for AES Core Based on Randomness , 2011 .

[3] Paul C. Kocher,et al. Differential Power Analysis , 1999, CRYPTO.

[4] Christof Paar,et al. Cryptographic Hardware and Embedded Systems - CHES 2003 , 2003, Lecture Notes in Computer Science.

[5] Christophe Clavier,et al. Correlation Power Analysis with a Leakage Model , 2004, CHES.

[6] Emmanuel Prouff,et al. Block Ciphers Implementations Provably Secure Against Second Order Side Channel Analysis , 2008, FSE.

[7] Paul C. Kocher,et al. Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems , 1996, CRYPTO.

[8] Stefan Mangard,et al. Power analysis attacks - revealing the secrets of smart cards , 2007 .

[9] Francis Olivier,et al. Electromagnetic Analysis: Concrete Results , 2001, CHES.