Constructing Effective UVM Testbench for DRAM Memory Controllers

In this paper, a general verification architecture for DRAM memory controllers is proposed. The proposed verification architecture is based on universal verification methodology (UVM) which makes use of the common features between different DRAM memory controllers to generate common and configurable scoreboard, sequences, stimulus, different UVM components, payload and test-cases. The proposed verification architecture uses minimum number of macros, methods and classes. The proposed verification architecture provides high reusability for UVM tests.