Properties of slow traps of ALD Al2O3/GeOx/Ge nMOSFETs with plasma post oxidation

The realization of Ge gate stacks with a small amount of slow trap density as well as thin equivalent oxide thickness and low interface state density (Dit) is a crucial issue for Ge CMOS. In this study, we examine the properties of slow traps, particularly the location of slow traps, of Al2O3/GeOx/n-Ge and HfO2/Al2O3/GeOx/n-Ge MOS interfaces with changing the process and structural parameters, formed by atomic layer deposition (ALD) of Al2O3 and HfO2/Al2O3 combined with plasma post oxidation. It is found that the slow traps can locate in the GeOx interfacial layer, not in the ALD Al2O3 layer. Furthermore, we study the time dependence of channel currents in the Ge n-MOSFETs with 5-nm-thick Al2O3/GeOx/Ge gate stacks, with changing the thickness of GeOx, in order to further clarify the position of slow traps. The time dependence of the current drift and the effective time constant of slow traps do not change among the MOSFETs with the different thickness GeOx, demonstrating that the slow traps mainly exist near the interfaces between Ge and GeOx.

[1]  Chunxiang Zhu,et al.  High mobility high-k/Ge pMOSFETs with 1 nm EOT -New concept on interface engineering and interface characterization , 2008, 2008 IEEE International Electron Devices Meeting.

[2]  Heiji Watanabe,et al.  First-principles study to obtain evidence of low interface defect density at Ge/GeO2 interfaces , 2009, 0904.2474.

[3]  Mitsuru Takenaka,et al.  Evidence of low interface trap density in GeO2∕Ge metal-oxide-semiconductor structures fabricated by thermal oxidation , 2008 .

[4]  A. Thean,et al.  Impact of starting measurement voltage relative to flat-band voltage position on the capacitance-voltage hysteresis and on the defect characterization of InGaAs/high-k metal-oxide-semiconductor stacks , 2015 .

[5]  J. Raskin,et al.  Temperature dependence of frequency dispersion in III–V metal-oxide-semiconductor C-V and the capture/emission process of border traps , 2015 .

[6]  A. Toriumi,et al.  Structural coordination of rigidity with flexibility in gate dielectric films for sub-nm EOT Ge gate stack reliability , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[7]  P.T. Lai,et al.  Improved Electrical Properties of Ge p-MOSFET With $ \hbox{HfO}_{2}$ Gate Dielectric by Using $\hbox{TaO}_{x} \hbox{N}_{y}$ Interlayer , 2008, IEEE Electron Device Letters.

[8]  Shinichi Takagi,et al.  Gate dielectric formation and MIS interface characterization on Ge , 2007 .

[9]  N. Taoka,et al.  High-Mobility Ge pMOSFET With 1-nm EOT $\hbox{Al}_{2} \hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stack Fabricated by Plasma Post Oxidation , 2012, IEEE Transactions on Electron Devices.

[10]  Mitsuru Takenaka,et al.  Al2O3/GeOx/Ge gate stacks with low interface trap density fabricated by electron cyclotron resonance plasma postoxidation , 2011 .

[11]  Krishna C. Saraswat,et al.  High performance germanium MOSFETs , 2006 .

[12]  H. Mertens,et al.  Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO2/HfO2 pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks , 2013, 2013 IEEE International Electron Devices Meeting.

[13]  S. Pantelides,et al.  Morphology and defect properties of the Ge–GeO2 interface , 2009 .

[14]  T. Tezuka,et al.  Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[15]  M. Takenaka,et al.  Impact of plasma post oxidation temperature on interface trap density and roughness at GeOx/Ge interfaces , 2013 .

[16]  Rui Zhang,et al.  High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using $\hbox{HfO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stacks Fabricated by Plasma Postoxidation , 2013, IEEE Transactions on Electron Devices.

[17]  D. L. Lile,et al.  The effect of interfacial traps on the stability of insulated gate devices on InP , 1983 .

[18]  K. Saraswat,et al.  Germanium MOS capacitors incorporating ultrathin high-/spl kappa/ gate dielectric , 2002, IEEE Electron Device Letters.

[19]  Marc Heyns,et al.  Effective electrical passivation of Ge(100) for high-k gate dielectric layers using germanium oxide , 2007 .

[20]  C. H. Lee,et al.  Oxygen potential engineering of interfacial layer for deep sub-nm EOT high-k gate stacks on Ge , 2013, 2013 IEEE International Electron Devices Meeting.

[21]  H. Mertens,et al.  BTI reliability of advanced gate stacks for Beyond-Silicon devices: Challenges and opportunities , 2014, 2014 IEEE International Electron Devices Meeting.

[22]  Tomonori Nishimura,et al.  Opportunities and challenges for Ge CMOS - Control of interfacing field on Ge is a key (Invited Paper) , 2009 .

[23]  Takeshi Kobayashi,et al.  Slow Current-Drift Mechanism in n-Channel Inversion Type InP-MISFET , 1980 .

[24]  S. Takagi,et al.  Fabrication and MOS interface properties of ALD AlYO3/GeOx/Ge gate stacks with plasma post oxidation , 2015 .

[25]  Mitsuru Takenaka,et al.  Surface orientation dependence of interface properties of GeO2/Ge metal-oxide-semiconductor structures fabricated by thermal oxidation , 2009 .

[26]  N. Taoka,et al.  1-nm-thick EOT high mobility Ge n- and p-MOSFETs with ultrathin GeOx/Ge MOS interfaces fabricated by plasma post oxidation , 2011, 2011 International Electron Devices Meeting.

[27]  C. Wilmsen,et al.  New model for slow current drift in InP metal‐insulator‐semiconductor field‐effect transistors , 1984 .