DraXRouter: global routing in X-architecture with dynamic resource assignment

In recent years, the X-architecture is introduced to obtain better performance for integrated circuit physical design. This paper reformulates the global routing problem in X-architecture under the liquid routing model. Then, a dynamic resource assignment (Dra) method is presented to reduce potential vias. At last, a global router called DraXRouter, is designed, in which we adopt a dynamic-tabulist-based tree construction algorithm and a stochastic optimization strategy to gain high quality routing solution. Tested on ISPD'98 benchmarks, DraXRouter achieves better routing performance compared with two recent global routers.

[1]  Majid Sarrafzadeh,et al.  An Introduction To VLSI Physical Design , 1996 .

[2]  Jun Gu,et al.  SSTT: Efficient local search for GSI global routing , 2003, Journal of Computer Science and Technology.

[3]  Chak-Kuen Wong,et al.  Hierarchical Steiner tree construction in uniform orientations , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Patrick H. Madden,et al.  Congestion reduction in traditional and new routing architectures , 2003, GLSVLSI '03.

[5]  Martin Zachariasen,et al.  A new paradigm for general architecture routing , 2004, GLSVLSI '04.

[6]  Cheng-Kok Koh,et al.  Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures , 2000, ACM Great Lakes Symposium on VLSI.

[7]  Hai Zhou,et al.  Spanning graph-based nonrectilinear steiner tree algorithms , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Xianlong Hong,et al.  An efficient rectilinear Steiner minimum tree algorithm based on ant colony optimization , 2004, 2004 International Conference on Communications, Circuits and Systems (IEEE Cat. No.04EX914).

[9]  Feng Zhou,et al.  Physical planning of on-chip interconnect architectures , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[10]  Yao-Wen Chang,et al.  Multilevel full-chip routing for the X-based architecture , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[11]  Yu Hu,et al.  A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design , 2005, SAMOS.

[12]  Steven L. Teig,et al.  The X architecture: not your father's diagonal wiring , 2002, SLIP '02.

[13]  Chung-Kuan Cheng,et al.  The Y-architecture: yet another on-chip interconnect solution , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

[14]  CQ出版株式会社.  Design Wave Magazine , 2005 .

[15]  Raia Hadsell,et al.  Improved global routing through congestion estimation , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[16]  David S. Johnson,et al.  The Complexity of Computing Steiner Minimal Trees , 1977 .