56Gs/s ADC : Enabling 100GbE
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A 100G coherent receiver needs 4 56Gs/s ADCs and a tera-OPs DSP which dissipate only tens of watts. This paper discusses the forces pushing towards a single-chip CMOS solution, and the challenges in realising this.
[1] Howard W. Johnson,et al. High Speed Signal Propagation: Advanced Black Magic , 2003 .