High-Frequency-Measurement-Based Circuit Modeling and Power/Ground Integrity Evaluation of Integrated Circuit Packages

The frequency-variant characteristics of a pair of package power and ground net are experimentally investigated and modeled by using frequency-variant grid-type equivalent circuits, where each cell of the grid is modeled with vertically stacked RLC-ladder circuits. Various test patterns are designed and fabricated by employing a ball grid array (BGA) package process. Then the test patterns are characterized by using impedance analyzer, time domain reflectometry and time domain transmission (TDR/TDT), and vector network analyzer (VNA). Based on the experimental characterizations, not only are material constants and circuit model parameters determined, but also the conductor roughness and other frequency-variant effects are modeled. It is shown that the SPICE-based circuit simulation using the proposed circuit model has an excellent agreement with the measurement data in the range of 100 MHz - 15 GHz. Then, it is also shown that the various types of package performance evaluations can be very efficiently as well as accurately achieved with the proposed technique.

[1]  Yungseon Eo,et al.  New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design , 2000, ECTC 2000.

[2]  Dennis Sylvester,et al.  Impact of small process geometries on microarchitectures in systems on a chip , 2001 .

[3]  Dong-Ho Han,et al.  Hybrid method for frequency-dependent lossy coupled transmission line characterization and modeling , 2003, Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).

[4]  Sharad Mehrotra,et al.  Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[5]  Nanju Na,et al.  Modeling and transient simulation of planes in electronic packages , 2000 .

[6]  David M. Pozar,et al.  Two Methods for the Measurement of Substrate Dielectric Constant , 1987 .

[7]  Wiren D. Becker,et al.  Power distribution modelling of high performance first level computer packages , 1993, Proceedings of IEEE Electrical Performance of Electronic Packaging.

[8]  John W. Poulton,et al.  Digital Systems Engineering: POWER DISTRIBUTION , 1998 .

[9]  J. L. Prince,et al.  Effect of CMOS driver loading conditions on simultaneous switching noise , 1994 .

[10]  I. Novak,et al.  Reducing simultaneous switching noise and EMI on ground/power planes by dissipative edge termination , 1998, IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.98TH8370).

[11]  William J. Dally,et al.  Digital systems engineering , 1998 .

[12]  D. P. Neikirk,et al.  Compact equivalent circuit model for the skin effect , 1996, 1996 IEEE MTT-S International Microwave Symposium Digest.

[13]  Keunmyung Lee,et al.  Modeling and analysis of multichip module power supply planes , 1995 .

[14]  W. R. Eisenstadt,et al.  High-speed VLSI interconnect modeling based on S-parameter measurements , 1993 .

[15]  Raymond E. Anderson,et al.  Power plane SPICE models and simulated performance for materials and geometries , 2001 .

[16]  S. R. Vemuru,et al.  Accurate simultaneous switching noise estimation including velocity-saturation effects , 1996 .

[17]  Madhavan Swaminathan,et al.  Modeling of multilayered power distribution planes using transmission matrix method , 2002 .