A high-speed ultra-low power 64K CMOS EPROM with on-chip test functions

A 100 ns 8K /spl times/ 8 CMOS EPROM has been developed. Internal clock signals generated by address transition detection are used to reduce power consumption. As a result, power dissipation is less than 5 mW/MHz in the active mode, and less than 1 /spl mu/W in both the standby mode and the active quiescent mode (chip enabled, but no address transitions sensed). Three special test features incorporated in the design can be used to reduce the time required for final test and reliability screening.

[1]  D. Frohman-Bentchkowsky,et al.  A fully-decoded 2048-bit electrically-programmable MOS ROM , 1971 .

[2]  J. E. Meyer,et al.  High-performance low-power CMOS memories using silicon-on-sapphire technology , 1972 .

[3]  Mitsuo Higuchi,et al.  A 150ns CMOS 64K EPROM using N-well technology , 1982 .

[4]  A. Renninger,et al.  A 64K EPROM using scaled MOS technology , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  K. Shirai,et al.  A 150ns 288k CMOS EPROM with redundancy , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  S. Kohyama,et al.  An ultralow power 8Kx8-bit full CMOS RAM with a six-transistor cell , 1982, IEEE Journal of Solid-State Circuits.