The AMD-K7 (TM) processor is an out-of-order, three-way superscalar x86 microprocessor with a 15-stage pipeline, organized to allow 500+MHz operation. The processor can fetch, decode, and retire up to three x86 instructions per cycle to independent integer and floating-point schedulers. The schedulers can simultaneously issue up to nine operations to seven integer and three floating point execution resources. The cache subsystem and memory interface minimize effective memory latency and provide high bandwidth data transfers to and from these execution resources. The processor contains separate instruction and data caches, each 64 kB and two-way set-associative. The data cache is banked and supports concurrent access by two loads or stores, each up to 64 b in length. The processor contains logic to directly control an external L2 cache. The L2 data interface is 64 b wide and supports bit rates up to 2/3 the processor clock rate. The system interface consists of a separate 64 b data bus.