Modern VLSI design : system-on-chip design/ Wayne Wolf

Preface to the Third Edition. Preface to the Second Edition. Preface. 1. Digital Systems and VLSI. Why Design Integrated Circuits? Integrated Circuit Manufacturing. CMOS Technology. Integrated Circuit Design Techniques. A Look into the Future. Summary. References. Problems. 2. Transistors and Layout. Introduction. Fabrication Processes. Transistors. Wires and Vias. Design Rules. Layout Design and Tools. References. Problems. 3. Logic Gates. Introduction. Combinational Logic Functions. Static Complementary Gates. Switch Logic. Alternative Gate Circuits. Low-Power Gates. Delay Through Resistive Interconnect. Delay Through Inductive Interconnect. References. Problems. 4. Combinational Logic Networks. Introduction. Standard Cell-Based Layout. Simulation. Combinational Network Delay. Logic and Interconnect Design. Power Optimization. Switch Logic Networks. Combinational Logic Testing. References. Problems. 5. Sequential Machines. Introduction. Latches and Flip-Flops. Sequential Systems and Clocking Disciplines. Sequential System Design. Power Optimization. Design Validation. Sequential Testing. References. Problems. 6. Subsystem Design. Introduction. Subsystem Design Principles. Combinational Shifters. Adders. ALUs. Multipliers. High-Density Memory. Field-Programmable Gate Arrays. Programmable Logic Arrays. References. Problems. 7. Floorplanning. Introduction. Floorplanning Methods. Off-Chip Connections. References. Problems. 8. Architecture Design. Introduction. Hardware Description Languages. Register-Transfer Design. High-Level Synthesis. Architectures for Low Power. Systems-on-Chips and Embedded CPUs. Architecture Testing. References. Problems. 9. Chip Design. Introduction. Design Methodologies. Kitchen Timer Chip. Microprocessor Data Path. References. Problems. 10. CAD Systems and Algorithms. Introduction. CAD Systems. Switch-Level Simulation. Layout Synthesis. Layout Analysis. Timing Analysis and Optimization. Logic Synthesis. Test Generation. Sequential Machine Optimizations. Scheduling and Binding. Hardware/Software Co-Design. References. Problems. Appendix A: A Chip Designer's Lexicon. Appendix B: Chip Design Projects. Class Project Ideas. Project Proposal and Specification. Design Plan. Design Checkpoints and Documentation. Appendix C: Kitchen Timer Model. Hardware Modeling in C. Index.