A 4-fJ/Spike Artificial Neuron in 65 nm CMOS Technology

As Moore's law reaches its end, traditional computing technology based on the Von Neumann architecture is facing fundamental limits. Among them is poor energy efficiency. This situation motivates the investigation of different processing information paradigms, such as the use of spiking neural networks (SNNs), which also introduce cognitive characteristics. As applications at very high scale are addressed, the energy dissipation needs to be minimized. This effort starts from the neuron cell. In this context, this paper presents the design of an original artificial neuron, in standard 65 nm CMOS technology with optimized energy efficiency. The neuron circuit response is designed as an approximation of the Morris-Lecar theoretical model. In order to implement the non-linear gating variables, which control the ionic channel currents, transistors operating in deep subthreshold are employed. Two different circuit variants describing the neuron model equations have been developed. The first one features spike characteristics, which correlate well with a biological neuron model. The second one is a simplification of the first, designed to exhibit higher spiking frequencies, targeting large scale bio-inspired information processing applications. The most important feature of the fabricated circuits is the energy efficiency of a few femtojoules per spike, which improves prior state-of-the-art by two to three orders of magnitude. This performance is achieved by minimizing two key parameters: the supply voltage and the related membrane capacitance. Meanwhile, the obtained standby power at a resting output does not exceed tens of picowatts. The two variants were sized to 200 and 35 μm2 with the latter reaching a spiking output frequency of 26 kHz. This performance level could address various contexts, such as highly integrated neuro-processors for robotics, neuroscience or medical applications.

[1]  S. Laughlin,et al.  An Energy Budget for Signaling in the Grey Matter of the Brain , 2001, Journal of cerebral blood flow and metabolism : official journal of the International Society of Cerebral Blood Flow and Metabolism.

[2]  Olivier Temam,et al.  Hardware spiking neurons design: Analog or digital? , 2012, The 2012 International Joint Conference on Neural Networks (IJCNN).

[3]  Jennifer Hasler,et al.  Finding a roadmap to achieve large neuromorphic hardware systems , 2013, Front. Neurosci..

[4]  Farzan Nadim,et al.  Membrane capacitance measurements revisited: dependence of capacitance value on measurement method in nonisopotential neurons. , 2009, Journal of neurophysiology.

[5]  W. Gerstner,et al.  Spike-Timing-Dependent Plasticity: A Comprehensive Overview , 2012, Front. Syn. Neurosci..

[6]  Narayan Srinivasa,et al.  A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. , 2012, Nano letters.

[7]  Stephen P. DeWeerth,et al.  Analogue VLSI Morris-Lecar neuron , 1997 .

[8]  F. Amzica,et al.  Membrane capacitance of cortical neurons and glia during sleep oscillations and spike-wave seizures. , 1999, Journal of neurophysiology.

[9]  Keechul Jung,et al.  GPU implementation of neural networks , 2004, Pattern Recognit..

[10]  Michael Rudolph,et al.  Inferring network activity from synaptic noise , 2004, Journal of Physiology-Paris.

[11]  Paul E. Hasler,et al.  A bio-physically inspired silicon neuron , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Arindam Basu,et al.  Nullcline-Based Design of a Silicon Neuron , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  J Joshua Yang,et al.  Memristive devices for computing. , 2013, Nature nanotechnology.

[14]  M. Mitchell Waldrop,et al.  The chips are down for Moore’s law , 2016, Nature.

[15]  Gert Cauwenberghs,et al.  Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics , 2010, IEEE Transactions on Biomedical Circuits and Systems.

[16]  Deepak Khosla,et al.  Spiking Deep Convolutional Neural Networks for Energy-Efficient Object Recognition , 2014, International Journal of Computer Vision.

[17]  G. Bi,et al.  Synaptic Modifications in Cultured Hippocampal Neurons: Dependence on Spike Timing, Synaptic Strength, and Postsynaptic Cell Type , 1998, The Journal of Neuroscience.

[18]  Dharmendra S. Modha,et al.  The cat is out of the bag: cortical simulations with 109 neurons, 1013 synapses , 2009, Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis.

[19]  Indranil Saha,et al.  journal homepage: www.elsevier.com/locate/neucom , 2022 .

[20]  Eugene M. Izhikevich,et al.  Which model to use for cortical spiking neurons? , 2004, IEEE Transactions on Neural Networks.

[21]  Kwabena Boahen,et al.  Learning in Silicon: Timing is Everything , 2005, NIPS.

[22]  A. Hodgkin,et al.  A quantitative description of membrane current and its application to conduction and excitation in nerve , 1952, The Journal of physiology.

[23]  Carver A. Mead,et al.  Neuromorphic electronic systems , 1990, Proc. IEEE.

[24]  A. van Schaik Building blocks for electronic spiking neural networks. , 2001, Neural networks : the official journal of the International Neural Network Society.

[25]  P. Lennie The Cost of Cortical Computation , 2003, Current Biology.

[26]  Farnood Merrikh-Bayat,et al.  Training and operation of an integrated neuromorphic network based on metal-oxide memristors , 2014, Nature.

[27]  Giacomo Indiveri,et al.  A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity , 2006, IEEE Transactions on Neural Networks.

[28]  C. Morris,et al.  Voltage oscillations in the barnacle giant muscle fiber. , 1981, Biophysical journal.

[29]  Massimo Alioto,et al.  Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[30]  Stefan Glasauer,et al.  Frequency-Domain Analysis of Intrinsic Neuronal Properties using High-Resistant Electrodes , 2009, Front. Neurom..

[31]  Gert Cauwenberghs,et al.  Neuromorphic Silicon Neuron Circuits , 2011, Front. Neurosci.

[32]  Carver Mead,et al.  Analog VLSI and neural systems , 1989 .

[33]  Piotr Dudek,et al.  Compact silicon neuron circuit with spiking and bursting behaviour , 2008, Neural Networks.

[34]  Chi-Sang Poon,et al.  Neuromorphic Silicon Neurons and Large-Scale Neural Networks: Challenges and Opportunities , 2011, Front. Neurosci..

[35]  Wolfgang Maass,et al.  Networks of Spiking Neurons: The Third Generation of Neural Network Models , 1996, Electron. Colloquium Comput. Complex..

[36]  Guigang Zhang,et al.  Deep Learning , 2016, Int. J. Semantic Comput..

[37]  Narayan Srinivasa,et al.  Energy-Efficient Neuron, Synapse and STDP Integrated Circuits , 2012, IEEE Transactions on Biomedical Circuits and Systems.

[38]  D. Wilkin,et al.  Neuron , 2001, Brain Research.

[39]  Eugene M. Izhikevich,et al.  Dynamical Systems in Neuroscience: The Geometry of Excitability and Bursting , 2006 .

[40]  Kwabena Boahen,et al.  Thermodynamically Equivalent Silicon Models of Voltage-Dependent Ion Channels , 2007, Neural Computation.

[41]  S. Schiff,et al.  Unification of Neuronal Spikes, Seizures, and Spreading Depression , 2014, The Journal of Neuroscience.