TRIP: An Automated Technology Mapping System

A technology mapping system, used for computer design in NEC, is presented. The features of this system are technology conversion and logical/physical optimization, based on a rule base, partitioning support, conversion verification and special layout consideration. This system is practically used for many applications for technology mapping, including redesigning an existing total unit into a new unit, based on up-to-date LSI technology. The resulting effect is quick inputting of integrated circuit technology progress into practical computer design area.

[1]  Shinichi Sato,et al.  Timing Verification System Based on Delay Time Hierarchical Nature , 1982, 19th Design Automation Conference.

[2]  Shigenobu Suzuki,et al.  Integrated Design System for Supercomputer SX-1/SX-2 , 1985, DAC 1985.

[3]  D. Brand,et al.  Technology Adaptation in Logic Synthesis , 1986, 23rd ACM/IEEE Design Automation Conference.

[4]  Louise Trevillyan,et al.  Technology adaption in logic synthesis , 1986, DAC.

[5]  Hidetoshi Tanaka,et al.  Logic Design Verification Using Automated Test Generation , 1984, ITC.

[6]  Tohru Sasaki,et al.  A High Level Test Pattern Generation Algorithm , 1983, ITC.

[7]  Louise Trevillyan,et al.  LSS: A system for production logic synthesis , 1984, IBM Journal of Research and Development.

[8]  J. B. Bendas.  Design Through Transformation , 1983, 20th Design Automation Conference Proceedings.

[9]  Takuji Ogihara,et al.  LORES-2: A Logic Reorganization System , 1985, IEEE Design & Test of Computers.

[10]  Bruce B. Winter,et al.  Automated Technology Mapping , 1984, IBM J. Res. Dev..

[11]  Shinichi Sato,et al.  Timing Verification System Based on Delay Time Hierarchical Nature , 1982, DAC 1982.

[12]  Koichiro Ishihara,et al.  POLARIS: Polarity Propagation Algorithm for Combinational Logic Synthesis , 1984, 21st Design Automation Conference Proceedings.