FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems

Algorithm-Architecture-Matching approach for iterative processing (“turbo” principle) in the digital communications systems can be applied for designing efficient architectures. In this context, rapid prototyping is an important step in the development and verification of architectural solutions. The goal is to replace time-consuming simulations based on abstract models of the system with realtime experiments under real-world conditions. In this paper, a flexible decoder architecture for turbo product code is first detailed. The major innovation involves the component code that is used by the product code. Indeed, the architecture is able to decode BCH and Reed-Solomon (RS) codes with single or double correction power. Implementation of the iterative decoder is done using a real-time FPGA prototyping board. The use of single-error-correcting RS product codes is also investigated in an ultra high-speed context. Thus, a fullparallel turbo decoding architecture dedicated to the (31, 29) RS product code has been designed and then implemented into a 5Gbps experimental setup. The purpose of this prototype is to demonstrate that RS turbo decoders can effectively achieve information rates above 1Gbps.

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