Superior PBTI Reliability for SOI FinFET Technologies and Its Physical Understanding

FinFETs provide a path for continued pitch and voltage scaling because of their excellent electrostatic short channel control. The key to design and optimization of FinFET technologies is to understand the differences of their reliability characteristics from those of planar devices. In this letter, we elucidate the differences in positive-bias temperature instability (PBTI) reliability between silicon-on-insulator nFinFETs and planar-bulk nFETs through experiments and TCAD modeling. We show that significantly improved PBTI for FinFET over planar-bulk at a given operating voltage arises from reduced vertical field. Furthermore, we show that the reduced field in FinFETs stems from less depletion charge in strong inversion associated with a fully depleted structure.

[1]  M. Rafik,et al.  28nm node bulk vs FDSOI reliability comparison , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[2]  C. Auth,et al.  A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[3]  Hyung-Kyu Lim,et al.  Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's , 1983, IEEE Transactions on Electron Devices.

[4]  E. Cartier,et al.  Bias temperature instability in High-κ/metal gate transistors - Gate stack scaling trends , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[5]  Huiming Bu.  FINFET technology a substrate perspective , 2011, IEEE 2011 International SOI Conference.

[6]  C. Cabral,et al.  A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[7]  A. Kerber,et al.  Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High- $k$ Stacks , 2009, IEEE Electron Device Letters.