论文信息 - Power and timing modeling for ASIC designs

Power and timing modeling for ASIC designs

This paper presents a unified power and timing modeling for ASIC libraries. This ASIC library is being standardized and targeted for a design flow, where timing analysis is complemented by power analysis. We show benchmark results from new industrial gate-level power analysis tools.

Wolfgang Roethig | A. M. Zarkesh | M. Andrews

[1] Hendrikus J. M. Veendrick,et al. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[2] Mary Jane Irwin,et al. Accurate Estimation of Combinational Circuit Activity , 1995, 32nd Design Automation Conference.

[3] Keshab K. Parhi,et al. HEAT: hierarchical energy analysis tool , 1996, DAC '96.

[4] Asim J. Al-Khalili,et al. A Module Generator for Optimized CMOS Buffers , 1989, 26th ACM/IEEE Design Automation Conference.