Physical limitation of the cascoded snapback NMOS ESD protection capability due to the non-uniform turn-off

The nonlinear effects and physical failure mechanism in over-voltage protection NMOS snapback structures during ESD operation have been analyzed with the use of experimental test structures as well as process and device simulations. A phenomenological explanation has been provided to account for the effect due to substrate type and the use of a so-called ESD implant. A generic design solution for the cascoded snapback NMOS structure suitable for 5-V tolerant I/O applications is proposed, one that delivers robust operation and eliminates the requirement for an additional ESD implant.

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