Silicon Wafer Map Defect Classification Using Deep Convolutional Neural Network With Data Augmentation

Wafer map defect classification is one of the most important process for semiconductor manufacturing. Wafer map defects are also cause of die failures. So, we propose a better method for classifying defects of wafer map. We propose deep convolutional neural network architecture and our proposed architecture is the improved version of previous researcher’s architecture. We also solve the data imbalance problem by applying data augmentation technique before training of data. The test accuracy of our research is 99.29% which is the best performance so far.

[1]  Peter König,et al.  Further Advantages of Data Augmentation on Convolutional Neural Networks , 2018, ICANN.

[2]  Heeyoung Kim,et al.  Classification of Mixed-Type Defect Patterns in Wafer Bin Maps Using Convolutional Neural Networks , 2018, IEEE Transactions on Semiconductor Manufacturing.

[3]  Jin Wang,et al.  Large-Scale Semiconductor Process Fault Detection Using a Fast Pattern Recognition-Based Method , 2010, IEEE Transactions on Semiconductor Manufacturing.

[4]  Seong-Jun Kim,et al.  Automatic Identification of Defect Patterns in Semiconductor Wafer Maps Using Spatial Correlogram and Dynamic Time Warping , 2008, IEEE Transactions on Semiconductor Manufacturing.

[5]  Geoffrey E. Hinton,et al.  ImageNet classification with deep convolutional neural networks , 2012, Commun. ACM.

[6]  Fei-Long Chen,et al.  A neural-network approach to recognize defect spatial pattern in semiconductor fabrication , 2000 .

[7]  Takeshi Nakazawa,et al.  Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network , 2018, IEEE Transactions on Semiconductor Manufacturing.

[8]  Suk Joo Bae,et al.  Detection of Spatial Defect Patterns Generated in Semiconductor Fabrication Processes , 2011, IEEE Transactions on Semiconductor Manufacturing.

[9]  Jimmy Ba,et al.  Adam: A Method for Stochastic Optimization , 2014, ICLR.

[10]  H. Hajj,et al.  Wafer Classification Using Support Vector Machines , 2012, IEEE Transactions on Semiconductor Manufacturing.

[11]  Kenneth W. Tobin,et al.  Automatic classification of spatial signatures on semiconductor wafer maps , 1997, Advanced Lithography.

[12]  Ming-Ju Wu,et al.  Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets , 2015, IEEE Transactions on Semiconductor Manufacturing.

[13]  Luis Perez,et al.  The Effectiveness of Data Augmentation in Image Classification using Deep Learning , 2017, ArXiv.

[14]  Way Kuo,et al.  Model-based clustering for integrated circuit yield enhancement , 2007, Eur. J. Oper. Res..

[15]  Geoffrey E. Hinton,et al.  Rectified Linear Units Improve Restricted Boltzmann Machines , 2010, ICML.