Low-Complexity Soft-Decision Concatenated LDGM-Staircase FEC for High-Bit-Rate Fiber-Optic Communication

A concatenated soft-decision forward error correction (FEC) scheme consisting of an inner low-density generator-matrix (LDGM) code and an outer staircase code is proposed. The soft-decision LDGM code is used for error reduction, while the majority of bit errors are corrected by the low-complexity hard-decision staircase code. Decoding complexity of the concatenated code is quantified by a score based on the number of edges in the LDGM code Tanner graph, the number of decoding iterations, and the number of staircase code decoding operations. The inner LDGM ensemble is designed by solving an optimization problem, which minimizes the product of the average node degree and an estimate of the required number of decoding iterations. A search procedure is used to find the inner and outer code pair with lowest complexity. The design procedure results in a Pareto-frontier characterization of the tradeoff between net coding gain and complexity for the concatenated code. Simulations of code designs at <inline-formula> <tex-math notation="LaTeX">$\text{20}\%$</tex-math></inline-formula> overhead showed that the proposed scheme achieves net coding gains equivalent to existing soft-decision FEC solutions, with up to <inline-formula> <tex-math notation="LaTeX">$\text{57}\%$</tex-math></inline-formula> reduction in complexity.

[1]  Stephen B. Wicker,et al.  Fundamentals of Codes, Graphs, and Iterative Decoding , 2002 .

[2]  Fan Yu,et al.  LDPC convolutional codes using layered decoding algorithm for high speed coherent optical transmission , 2012, OFC/NFOEC.

[3]  Laurent Schmalen,et al.  Spatially Coupled Soft-Decision Error Correction for Future Lightwave Systems , 2015, Journal of Lightwave Technology.

[4]  Wei Yu,et al.  Design of irregular LDPC codes with optimized performance-complexity tradeoff , 2010, IEEE Transactions on Communications.

[5]  Jonathan S. Yedidia,et al.  Rateless codes on noisy channels , 2004, International Symposium onInformation Theory, 2004. ISIT 2004. Proceedings..

[6]  Masoud Ardakani,et al.  A more accurate one-dimensional analysis and design of irregular LDPC codes , 2004, IEEE Transactions on Communications.

[7]  Fan Mo,et al.  Soft-decision forward error correction in a 40-nm ASIC for 100-Gbps OTN applications , 2011, 2011 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference.

[8]  Yoshiaki Konishi,et al.  Soft-Decision-Based Forward Error Correction for 100 Gb/s Transport Systems , 2010, IEEE Journal of Selected Topics in Quantum Electronics.

[9]  D.E. Hocevar,et al.  A reduced complexity decoder architecture via layered decoding of LDPC codes , 2004, IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004..

[10]  Mario Rafael Hueda,et al.  Non-Concatenated FEC Codes for Ultra-High Speed Optical Transport Networks , 2011, 2011 IEEE Global Telecommunications Conference - GLOBECOM 2011.

[11]  Kenya Sugihara,et al.  A spatially-coupled type LDPC Code with an NCG of 12 dB for optical transmission beyond 100 Gb/s , 2013, 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC).

[12]  Yongyi Mao,et al.  On the design of raptor codes for binary-input gaussian channels , 2009, IEEE Trans. Commun..

[13]  Omid Etesami,et al.  Raptor codes on binary memoryless symmetric channels , 2006, IEEE Transactions on Information Theory.

[14]  Marios C. Papaefthymiou,et al.  27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[15]  Stephan ten Brink,et al.  Design of low-density parity-check codes for modulation and detection , 2004, IEEE Transactions on Communications.

[16]  In-Cheol Park,et al.  A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory , 2013, IEEE Journal of Solid-State Circuits.

[17]  Michael Luby,et al.  LT codes , 2002, The 43rd Annual IEEE Symposium on Foundations of Computer Science, 2002. Proceedings..

[18]  Philippe Flatresse,et al.  27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[19]  Takashi Mizuochi,et al.  Performance improvement of a triple-concatenated FEC by a UEP-BCH product code for 100 Gb/s optical transport networks , 2013, 2013 18th OptoElectronics and Communications Conference held jointly with 2013 International Conference on Photonics in Switching (OECC/PS).

[20]  In-Cheol Park,et al.  7.3 Gb/s universal BCH encoder and decoder for SSD controllers , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[21]  Frank R. Kschischang,et al.  Staircase Codes: FEC for 100 Gb/s OTN , 2012, Journal of Lightwave Technology.

[22]  Frank R. Kschischang,et al.  Staircase Codes With 6% to 33% Overhead , 2014, Journal of Lightwave Technology.

[23]  Yang Li,et al.  FPGA verification of a single QC-LDPC code for 100 Gb/s optical systems without error floor down to BER of 10−15 , 2011, 2011 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference.

[24]  Sae-Young Chung,et al.  Analysis of sum-product decoding of low-density parity-check codes using a Gaussian approximation , 2001, IEEE Trans. Inf. Theory.

[25]  Daniel A. Spielman,et al.  Linear-time encodable and decodable error-correcting codes , 1995, STOC '95.

[26]  Alexandre Graell i Amat,et al.  Terminated and Tailbiting Spatially Coupled Codes With Optimized Bit Mappings for Spectrally Efficient Fiber-Optical Systems , 2014, Journal of Lightwave Technology.