Electron beam direct writing (EBDW) system is at the head of systems fabricating circuit patterns by maskless. But the throughput of EBDW is very poor beause very large number of electron beam (EB) shots are requested for exposure of whole patterns on a wafer. We had proposed methods of reduction of the number of EB shots with Character Projection (CP) and designing the best devicve pattern for CP-EBDW to fabricate logic devices such as ASIC or SoC device. Though the method is effective to Front-End-Of-Line (FEOL) layers of cell based logic deviec, Back-End-Of-Line (BEOL) layers cannot be exposed by the method with small number of characters and EB shots. Now, we will propose methods for appropriate CP exposure and data processign for patterns in BEOL layers. By the methods, each BEOL layer in a typical logic device cna be exposed with throughputs about 6 to 8 wafers/h, with a Low-energy-EBDW system produced by e-BEAM Corporation, named "EBIS".