80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications

Automotive, Artificial Intelligence/Machine Learning and blockchain generation are imposing increasing demanding specs for Dynamic Random Access Memory (DRAM) memories. Wider memory bandwidth can be achieved by using conventional planar SiO2 MOSFET and different interfaces but at the expense of required energy per bit. Advantages of High-K/Metal Gate versus SiO2/SiON planar DRAM periphery devices compatible with DRAM memory fabrication have been demonstrated in literature. More recently, the power performance benefit of FinFET for DRAM peri devices have been discussed. In this paper we provide a detailed analysis and additional insights in the first experimental validation of a thermally stable, reliable and cost effective tall fins platform (65 and 80 nm fin height). Power performance benefit versus fin height and expected area advantages on Sense Amp area are presented.

[1]  J. Ryckaert,et al.  Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[2]  E. Simoen,et al.  A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies , 2014, 2014 IEEE International Electron Devices Meeting.

[3]  R. Ritzenthaler,et al.  Optimized material solutions for advanced DRAM peripheral transistors , 2016 .

[4]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[5]  G. Ghibaudo,et al.  High Threshold Voltage Matching Performance on Gate-All-Around MOSFET , 2007, 2006 European Solid-State Device Research Conference.

[6]  A. Asenov.  Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study , 1998 .

[7]  R. Ritzenthaler,et al.  Reliability Engineering Enabling Continued Logic for Memory Device Scaling , 2019, 2019 IEEE International Integrated Reliability Workshop (IIRW).

[8]  Jong-Ho Lee,et al.  A Fully Integrated Low Voltage DRAM with Thermally Stable Gate-first High-k Metal Gate Process , 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

[9]  R. Ritzenthaler,et al.  Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks , 2013 .

[10]  Alessio Spessot,et al.  1T-1C Dynamic Random Access Memory Status, Challenges, and Prospects , 2020, IEEE Transactions on Electron Devices.

[11]  Naoto Horiguchi,et al.  A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond , 2014, IEEE Transactions on Electron Devices.

[12]  Seong Keun Kim,et al.  Future of dynamic random-access memory as main memory , 2018 .

[13]  R. Ritzenthaler,et al.  Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability , 2020, IEEE Transactions on Device and Materials Reliability.

[14]  Kinam Kim,et al.  DRAM technology perspective for gigabit era , 1998 .

[15]  C. Auth,et al.  A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[16]  Sung-Joo Hong,et al.  Gate-first high-k/metal gate DRAM technology for low power and high performance products , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[17]  Thomas Skotnicki,et al.  High Threshold Voltage Matching Performance on Gate-All-Around MOSFET , 2006 .