Network-on-Chip Programmable Platform in VersalTM ACAP Architecture

This paper outlines the Network-on-Chip (NoC) on Xilinx's next generation Versal-architecture. It is a hardened NoC that is present in Xilinx's next-generation 7nm architecture devices. These devices include many other new hardened features that make up the Adaptable Computing Acceleration Platform (ACAP) devices. There is a trend in FPGA devices of hardening many commonly used components such as processors, memory controllers and other IO controllers. The next generation of Xilinx devices take this a step further by providing a device-global memory mapped NoC which connects these components and the fabric in an integrated fashion. The NoC unifies communication between the processor system, FPGA fabric, memory subsystem and other hardened accelerator functions. This paper gives an overview of the Versal architecture NoC. It also motivates some of the specific characteristics of the architecture. We show how hardening the NoC lets users quickly implement high performance system level interconnect.

[1]  Idit Keidar,et al.  NoC-Based FPGA: Architecture and Routing , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[2]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[3]  Jean-Jacques Lecler,et al.  Application driven network-on-chip architecture exploration & refinement for a complex SoC , 2011, Des. Autom. Embed. Syst..

[4]  M. Bohr.  Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.

[5]  Leonard Kleinrock,et al.  Reprint of "Virtual cut-through: A new computer communication switching technique" , 2014, Comput. Networks.

[6]  James C. Hoe,et al.  CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs , 2012, FPGA '12.

[7]  Keith Kim,et al.  HBM (High Bandwidth Memory) DRAM Technology and Architecture , 2017, 2017 IEEE International Memory Workshop (IMW).

[8]  Vaughn Betz,et al.  The Case for Embedded Networks on Chip on Field-Programmable Gate Arrays , 2014, IEEE Micro.

[9]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[10]  Hari Angepat,et al.  A cloud-scale acceleration architecture , 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[11]  Ranga Vemuri,et al.  LiPaR: A light-weight parallel router for FPGA-based networks-on-chip , 2005, ACM Great Lakes Symposium on VLSI.

[12]  Lionel M. Ni,et al.  A survey of wormhole routing techniques in direct networks , 1993, Computer.

[13]  André DeHon,et al.  FPGA optimized packet-switched NoC using split and merge primitives , 2012, 2012 International Conference on Field-Programmable Technology.

[14]  Valavan Manohararajah,et al.  The Stratix™ 10 Highly Pipelined FPGA Architecture , 2016, FPGA.

[15]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[16]  William J. Dally,et al.  Virtual-channel flow control , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

[17]  Shant Chandrakar,et al.  Enhancements in UltraScale CLB Architecture , 2015, FPGA.

[18]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[19]  Nachiket Kapre,et al.  Hoplite: Building austere overlay NoCs for FPGAs , 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

[20]  Simon W. Moore,et al.  Exploring hard and soft networks-on-chip for FPGAs , 2008, 2008 International Conference on Field-Programmable Technology.

[21]  R. Chaware,et al.  Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.