论文信息 - The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI

The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI

Circuit requirements of scaled devices based on noise margin, parameter variation, parasitic resistance and drift velocity saturation lead to non-constant field scaling, which predict a maximum in performance as devices are scaled. This maximum occurs at a smaller length for p-channel than for n-channel for a given scaling rule, and causes the performance of the two to approach each other at L<0.3µm. The p-channel devices under these conditions are shown to be 100x less effected by hot carriers induced reliability problems than n-channel devices.

P. Chatterjee | W. Hunter | T. Holloway | Y.T. Lin

[1] R. A. Logan,et al. Ionization Rates of Holes and Electrons in Silicon , 1964 .

[2] K. Steinhubl. Design of Ion-Implanted MOSFET'S with Very Small Physical Dimensions , 1974 .

[3] C. Jacoboni,et al. A review of some charge transport properties of silicon , 1977 .

[4] P.K. Chatterjee,et al. VLSI Dynamic nMOS design constraints due to drain induced primary and secondary impact ionization , 1979, 1979 International Electron Devices Meeting.

[5] J. T. Clemens,et al. Characterization of the electron mobility in the inverted <100> Si surface , 1979, 1979 International Electron Devices Meeting.

[6] T. Mano,et al. A 256K RAM fabricated with molybdenum-polysilicon technology , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.