5 GHz 1.4 dB NF CMOS LNA integrated in 130 nm High Resistivity SOI technology

CMOS is today a good candidate for an optimum single chip implementation of both the analog and digital blocks in wireless mobile transceivers. Concerning analog RF blocks, SOI CMOS offer advantages over CMOS bulk, such as reduced source/drain-substrate capacitance and elimination of body effect which are suited for low voltage supply. Furthermore, SOI offers the opportunity to use high resistivity substrate leading to high performances planar inductor and better substrate insulation. In this work, the design of a 5 GHz WLAN LNA in a 0.13 mum SOI CMOS technology using High Resistivity substrate (HR) is discussed. State-of-the-art NF of 1.4 db@ 5 GHz and gain of 14 dB @5 GHz are reported for a consumption of 8 mA under 1.2 V.

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