PHRYCTORIA: A Messaging System for Transprecision OpenCAPI-attached FPGA Accelerators

Messaging frameworks are prevalent in distributed software systems as they simplify the exchange of data between applications running on different platforms. Messages are serialized and deserialized to transform user data structures into binary data for sending across the network. In a similar spirit, modern heterogenous computing platorms typically containing FPGAs can also profit from such messaging frameworks. Efficient compact serialization of data types is needed to take full advantage of the high throughput communication links. Transprecision extensions of FPGA replace native data types with novel low-precision data types. Transprecision extensions are shown to result in less-compact serializations. In this paper, we present a messaging framework for transprecision hardware accelerators which supports messages expressed in Protobuf and automatically generates serialization and deserialization functions. Our messageing framework leverages the varint encoding of Protocol buffers for efficient serialization and deserialization of transprecision data types. Evaluation results show that it can increase the effective throughput of OpenCAPI by up to $7.4 \times $ for various transprecision data-types.

[1]  Heiner Giefers,et al.  Extending the POWER Architecture with Transprecision Co-Processors , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[2]  Xin Fang,et al.  Open-Source Variable-Precision Floating-Point Library for Major Commercial FPGAs , 2016, ACM Trans. Reconfigurable Technol. Syst..

[3]  Luca Benini,et al.  A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[4]  Sizhuo Zhang,et al.  HGum: Messaging framework for hardware accelerators , 2017, 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

[5]  James C. Hoe,et al.  CoRAM: an in-fabric memory architecture for FPGA-based computing , 2011, FPGA '11.

[6]  Heiner Giefers,et al.  Accelerating arithmetic kernels with coherent attached FPGA coprocessors , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[7]  Enrique S. Quintana-Ortí,et al.  FloatX , 2019, ACM Trans. Math. Softw..

[8]  Christoph Hagleitner,et al.  Network-attached FPGAs for data center applications , 2016, 2016 International Conference on Field-Programmable Technology (FPT).

[9]  Christoph Hagleitner,et al.  A System-Level Transprecision FPGA Accelerator for BLSTM Using On-chip Memory Reshaping , 2018, 2018 International Conference on Field-Programmable Technology (FPT).

[10]  H. Peter Hofstee,et al.  Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow , 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).