General Characterization Method and a Fast Load-Charge-Preserving Switching Procedure for the Stepwise Adiabatic Circuits

An analytical method is presented to characterize stepwise adiabatic circuits (SACs). In this method, the SACs are modeled as a discrete time system. Unlike previous methods, the stability is verified for arbitrary load capacitor ratios. Moreover, this method presents analytical derivations to offer an area/energy efficient design methodology. MATLAB simulations, post-layout simulations in the CMOS 0.18 μm technology, silicon measurements, and measurements based on discrete components confirm the precision of the analytical derivations. Using the proposed design methodology, a capacitive tank has been designed which reduces the energy consumption by 20% while the total size of the tank capacitors is smaller than 0.4CL. Additionally, a new switching procedure for the SACs is presented. This procedure stabilizes the voltage levels without reverse switching, unlike previously reported methods. Thus preserving the energy efficiency, it improves the speed by a factor of up to two, since the tank recycles its charge inherently. Moreover, the capacitive load can retain its charge after the charging process and let the tank charges another load capacitor. As a result, the proposed switching procedure can be used in multi-cycle circuits such as the capacitive DAC of a SAR ADC in which the load capacitor must hold its charge after charging process is finished.

[1]  G.H.S. Rokos Comment: Voltage amplification in switched-capacitor networks , 1981 .

[2]  P. V. Ananda Mohan,et al.  Switched Capacitor Filters: Theory, Analysis and Design , 1995 .

[3]  Shunji Nakata The stability of adiabatic reversible logic using asymmetric tank capacitors and its application to SRAM , 2005, IEICE Electron. Express.

[4]  I. Cederbaum Voltage amplification in switched-capacitor networks , 1981 .

[5]  V.S. Sathe,et al.  Resonant-Clock Latch-Based Design , 2008, IEEE Journal of Solid-State Circuits.

[6]  Hyung-Soo Mok,et al.  A load commutated inverter-fed induction motor drive system using a novel DC-side commutation circuit , 1994 .

[7]  Yasuhiro Takahashi,et al.  4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR , 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

[8]  Ata Khorami,et al.  Elimination of the effect of bottom-plate capacitors in C-2C DAC using a layout technique , 2015, Microelectron. J..

[9]  Kaushik Roy,et al.  Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Ka-Ming Keung,et al.  A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  W. Athas,et al.  A low-power adiabatic driver system for AMLCDs , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[12]  Shunji Nakata,et al.  General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Ata Khorami,et al.  Zero-power mismatch-independent digital to analog converter , 2015 .

[14]  Shunji Nakata,et al.  Adiabatic SRAM with a large margin of VT variation by controlling the cell-power-line and word-line voltage , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[15]  John Stewart Denker,et al.  Adiabatic dynamic logic , 1995 .

[16]  Shunji Nakata,et al.  Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[17]  Shunji Nakata Stability of adiabatic reversible charging using 1D-capacitor array between the power supply and ground , 2007, IEICE Electron. Express.

[18]  Ata Khorami,et al.  One-dimensional adiabatic circuits with inherent charge recycling , 2015 .

[19]  Jiaoyan Chen,et al.  Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations , 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

[20]  Shunji Nakata,et al.  Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation , 2010, IEICE Electron. Express.

[21]  Deog-Kyoon Jeong,et al.  An efficient charge recovery logic circuit , 1996, IEEE J. Solid State Circuits.

[22]  L. J. Svensson,et al.  Driving a capacitive load without dissipating fCV/sup 2/ , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[23]  Eric A. M. Klumperink,et al.  A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s , 2010, IEEE Journal of Solid-State Circuits.

[24]  Yasuhiro Takahashi,et al.  Low-power adiabatic SRAM , 2011, 2011 International Symposium on Intelligent Signal Processing and Communications Systems (ISPACS).