Run-Time Computation and Communication Aware Mapping Heuristic for NoC-Based Heterogeneous MPSoC Platforms

The rapid increase in the complexity of real-life applications has led to the perpetual demand of refined architectural designs. Multiprocessor systems-on-chip (MPSoC) emerges as one of the possible solution for satiating such enormous computational needs. These MPSoCs are employed with Network-On-Chip (NoC) interconnect for power efficient and scalable inter-communication required between processors. Mapping parallelized tasks of applications onto these MPSoCs is the next gigantic problem, which can be done either at design-time or at run-time. However, design-time strategies may sometimes provide a more optimal mapping but they are restricted to predefined set of applications and seem incapable of run-time resource management. On the contrary, run-time mapping techniques overcome this limitation by determining the state of the platform and incorporating resource management before mapping. This paper describes a heuristic for run-time mapping of parallelized tasks of an application considering efficient computation, communication and resource utilization as the main parameters for optimization.

[1]  Ahmad Khademzadeh,et al.  DSM: A Heuristic Dynamic Spiral Mapping algorithm for network on chip , 2008, IEICE Electron. Express.

[2]  E. Carvalho,et al.  Congestion-aware task mapping in heterogeneous MPSoCs , 2008, 2008 International Symposium on System-on-Chip.

[3]  Jörg Henkel,et al.  On-chip networks: a scalable, communication-centric embedded system design paradigm , 2004, 17th International Conference on VLSI Design. Proceedings..

[4]  Fabrizio Petrini,et al.  Cell Multiprocessor Communication Network: Built for Speed , 2006, IEEE Micro.

[5]  Srinivasan Murali,et al.  A Methodology for Mapping Multiple Use-Cases onto Networks on Chips , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[6]  Petru Eles,et al.  Scheduling and mapping of conditional task graph for the synthesis of low power embedded systems , 2003 .

[7]  Diederik Verkest,et al.  Run-Time Management of a MPSoC Containing FPGA Fabric Tiles , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Pier Luca Lanzi,et al.  Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems , 2009, GECCO '09.

[9]  Daniël Paulusma,et al.  Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[10]  Lothar Thiele,et al.  Power-Aware Mapping of Probabilistic Applications onto Heterogeneous MPSoC Platforms , 2009, 2009 15th IEEE Real-Time and Embedded Technology and Applications Symposium.

[11]  Jing-Yang Jou,et al.  Communication-driven task binding for multiprocessor with latency insensitive network-on-chip , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[12]  Amit Kumar Singh,et al.  Efficient Heuristics for Minimizing Communication Overhead in NoC-based Heterogeneous MPSoC Platforms , 2009, 2009 IEEE/IFIP International Symposium on Rapid System Prototyping.

[13]  Gerard J. M. Smit,et al.  Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC) , 2007, 2008 Design, Automation and Test in Europe.

[14]  Hannu Tenhunen,et al.  Guest Editors' Introduction: Multiprocessor Systems-on-Chips , 2005, Computer.

[15]  Flávio Rech Wagner,et al.  Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications , 2008, 2008 Design, Automation and Test in Europe.

[16]  David Wentzlaff,et al.  Processor: A 64-Core SoC with Mesh Interconnect , 2010 .

[17]  Amit Kumar Singh,et al.  Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms , 2010, J. Syst. Archit..

[18]  Fernando Gehm Moraes,et al.  Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs , 2007, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07).

[19]  Petru Eles,et al.  Scheduling and mapping of conditional task graphs for the synthesis of low power embedded systems , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[20]  L. Carro,et al.  Time and energy efficient mapping of embedded applications onto NoCs , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[21]  Lothar Thiele,et al.  Mapping Applications to Tiled Multiprocessor Embedded Systems , 2007, Seventh International Conference on Application of Concurrency to System Design (ACSD 2007).