Using Synchronized Transitions for Simulation and Timing Verification

Synchronized Transitions is a formal notation for hardware speciication, veriica-tion, and simulation. This paper describes the use of Synchronized Transitions in the design of a chip for high bandwidth interprocessor communication. The chip uses a hybrid of synchronous and self-timed circuit techniques; a proof is presented that all timing requirements are satissed. The Synchronized Transitions notation is presented , and it is shown how programs can be translated into logic predicates, providing a basis for formal veriication. The use of Synchronized Transitions in the simulation of the chip is described, and the design choices of using both simulation and formal proofs are discussed.