Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications
暂无分享,去创建一个
Baker Mohammad | Hani H. Saleh | Mahmoud Al-Qutayri | Yasmin Halawani | Dirar Homouz | M. Al-Qutayri | D. Homouz | B. Mohammad | H. Saleh | Y. Halawani
[1] Said Hamdioui,et al. Alternative Architectures Toward Reliable Memristive Crossbar Memories , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[2] C. Toumazou,et al. A Versatile Memristor Model With Nonlinear Dopant Kinetics , 2011, IEEE Transactions on Electron Devices.
[3] E. Belhaire,et al. Macro-model of Spin-Transfer Torque based Magnetic Tunnel Junction device for hybrid Magnetic-CMOS design , 2006, 2006 IEEE International Behavioral Modeling and Simulation Workshop.
[4] Weimin Zhou,et al. Application of NIL in Memory Devices , 2013 .
[5] Lipeng Wan,et al. System Architecture and Operating Systems , 2014 .
[6] Linda M. Engelbrecht. Modeling spintronics devices in Verilog-A for use with industry-standard simulation tools , 2011 .
[7] Baker Mohammad,et al. Robust Hybrid Memristor-CMOS Memory: Modeling and Design , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[8] Sub-Nanosecond Precessional Switching in a MRAM Cell with a Perpendicular Polarizer , 2012, 2012 4th IEEE International Memory Workshop.
[9] R. Williams,et al. Exponential ionic drift: fast switching and low volatility of thin-film memristors , 2009 .
[10] Shamik Das,et al. Switching-time analysis of binary-oxide memristors via a nonlinear model , 2012 .
[11] A.P. Chandrakasan,et al. A 10-pJ/instruction, 4-MIPS micropower DSP for sensor applications , 2008, 2008 IEEE Asian Solid-State Circuits Conference.
[12] Antonio Rubio,et al. Reliability challenges in design of memristive memories , 2014, 2014 5th European Workshop on CMOS Variability (VARI).
[13] R. Williams,et al. Coupled ionic and electronic transport model of thin-film semiconductor memristive behavior. , 2009, Small.
[14] Baker Mohammad. Embedded Memory Design for Multi-Core and Systems on Chip , 2013 .
[15] Baker Mohammad,et al. Modeling of STT-MTJ for low power embedded memory applications: A comparative review , 2013, 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS).
[16] S. Ha,et al. Adaptive oxide electronics: A review , 2011 .
[17] K. Roy,et al. Physics-Based SPICE-Compatible Compact Model for Simulating Hybrid MTJ/CMOS Circuits , 2013, IEEE Transactions on Electron Devices.
[18] Mircea R. Stan,et al. Relaxing non-volatility for fast and energy-efficient STT-RAM caches , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.
[19] S. Narendra,et al. Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.
[20] Winston K. G. Seah,et al. Sustainable Wireless Sensor Networks , 2010 .
[21] Peter Desnoyers,et al. Ultra-low power data storage for sensor networks , 2009, TOSN.
[22] Amirali Ghofrani,et al. Towards data reliable crossbar-based memristive memories , 2013, 2013 IEEE International Test Conference (ITC).
[23] Kyoung-Rok Cho,et al. Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[24] Livio Baldi,et al. Emerging memories , 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).
[25] Nathan Ickes,et al. A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).
[26] Donghyun Kim,et al. Embedded Memory Architecture for Low-Power Application Processor , 2009 .
[27] Anantha Chandrakasan,et al. Challenges and Directions for Low-Voltage SRAM , 2011, IEEE Design & Test of Computers.
[28] Sally A. McKee,et al. Memory Wall , 2011, Encyclopedia of Parallel Computing.
[30] Seung H. Kang,et al. Development of Embedded STT-MRAM for Mobile System-on-Chips , 2011, IEEE Transactions on Magnetics.
[31] D. Nikonov,et al. Strategies and tolerances of spin transfer torque switching , 2010, 1001.4578.
[32] J. Tour,et al. Electronics: The fourth element , 2008, Nature.
[33] Claude Chappert,et al. Dynamic compact model of Spin-Transfer Torque based Magnetic Tunnel Junction (MTJ) , 2009, 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era.
[34] Weng-Fai Wong,et al. STT-RAM Cache Hierarchy With Multiretention MTJ Designs , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[35] Los Angeles,et al. Energy-Performance Characterization of CMOS/Magnetic Tunnel Junction (MTJ) Hybrid Logic Circuits , 2011 .
[36] K. Goodson,et al. Temperature-Dependent Thermal Properties of Phase-Change Memory Electrode Materials , 2011, IEEE Electron Device Letters.
[37] Stephen J. Wolf,et al. The elusive memristor: properties of basic electrical circuits , 2008, 0807.3994.
[38] J. Yang,et al. Memristive switching mechanism for metal/oxide/metal nanodevices. , 2008, Nature nanotechnology.
[39] Matthew D. Pickett,et al. Physics-based memristor models , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).
[40] J Joshua Yang,et al. Memristive devices for computing. , 2013, Nature nanotechnology.
[41] J. Tschanz,et al. Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances , 2011, IEEE Transactions on Electron Devices.
[42] R. Williams,et al. Measuring the switching dynamics and energy efficiency of tantalum oxide memristors , 2011, Nanotechnology.
[43] Elfed Lewis,et al. A comparative review of wireless sensor network mote technologies , 2009, 2009 IEEE Sensors.
[44] Weisheng Zhao,et al. Compact Modeling of Perpendicular-Anisotropy CoFeB/MgO Magnetic Tunnel Junctions , 2012, IEEE Transactions on Electron Devices.
[45] Chita R. Das,et al. Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs , 2012, DAC Design Automation Conference 2012.