CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator

This paper describes a low voltage, low jitter clock synthesizer and a temperature compensated tunable oscillator. Both of these circuits employ a self-correcting Delay Locked Loop (DLL). The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer and provides temperature compensated biasing for the tunable oscillator. With a 2 V supply the measured RMS jitter for the 1 GHz synthesizer output was 3.2 ps. With a 3.3 V supply RMS jitter of 3.1 ps was measured for a 1.6 GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0 to 85/spl deg/C. The circuits were fabricated on a generic 0.5 /spl mu/m digital CMOS process.

[1]  Keng L. Wong,et al.  A PLL clock generator with 5 to 110 MHz of lock range for microprocessors , 1992 .

[2]  Behzad Razavi,et al.  PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design , 1996 .

[3]  John G. Maneatis.  PLL Based on Self-Biased Techniques , 1996 .

[4]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[5]  H. C. Yang,et al.  A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation , 1997 .

[6]  Stefanos Sidiropoulos,et al.  A semidigital dual delay-locked loop , 1997, IEEE J. Solid State Circuits.

[7]  Mark Horowitz,et al.  High-speed electrical signaling: overview and limitations , 1998, IEEE Micro.

[8]  H. Chen,et al.  A 2 GHz VCO with process and temperature compensation , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[9]  M. Mota,et al.  A high-resolution time interpolator based on a delay locked loop and an RC delay line , 1999, IEEE J. Solid State Circuits.

[10]  D. Jeong,et al.  A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[11]  Deog-Kyoon Jeong,et al.  An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance , 2000, IEEE Journal of Solid-State Circuits.

[12]  G. Chien,et al.  A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications , 2000, IEEE Journal of Solid-State Circuits.

[13]  A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[14]  David J. Foley,et al.  CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator , 2001 .