Novel high efficiency multilevel DC-DC boost converter topologies and modulation strategies

In this paper new topologies and interleaving modulation concepts for multilevel DC-DC boost converter enabling a significantly less loss and a reduced chip size of the power semiconductors are proposed. Moreover, a new soft switching concept is presented. The achievable efficiency, chip area and boost inductance reduction are compared with existing solutions for V<inf>In</inf> = 800V, V<inf>Out</inf> = 3kV and P<inf>Out</inf> = 150 kW. A 30% loss reduction and a chip area decrease by 50% is achieved.

[1]  G. Ledwich,et al.  A new configuration for multilevel converters with diode clamped topology , 2007, 2007 International Power Engineering Conference (IPEC 2007).

[2]  Johann W. Kolar,et al.  Optimal design of resonant converter for Electrostatic Precipitators , 2010, The 2010 International Power Electronics Conference - ECCE ASIA -.

[3]  J.W. Kolar,et al.  Optimized Pulse Patterns for the 5-Level ANPC Converter for High Speed High Power Applications , 2006, IECON 2006 - 32nd Annual Conference on IEEE Industrial Electronics.

[4]  M. Schweizer,et al.  Comparison and implementation of a 3-level NPC voltage link back-to-back converter with SiC and Si diodes , 2010, 2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC).

[5]  Dushan Boroyevich,et al.  A comprehensive study of neutral-point voltage balancing problem in three-level neutral-point-clamped voltage source PWM inverters , 2000 .

[6]  T. Friedli,et al.  A Semiconductor Area Based Assessment of AC Motor Drive Converter Topologies , 2009, 2009 Twenty-Fourth Annual IEEE Applied Power Electronics Conference and Exposition.

[7]  Johann W. Kolar,et al.  Comparison of the chip area usage of 2-level and 3-level voltage source converter topologies , 2010, IECON 2010 - 36th Annual Conference on IEEE Industrial Electronics Society.

[8]  I. Barbi,et al.  Three-level quadratic non-insulated basic DC-DC converters , 2007, 2007 European Conference on Power Electronics and Applications.

[9]  J. Rodriguez,et al.  NPC multilevel multistring topology for large scale grid connected photovoltaic systems , 2010, The 2nd International Symposium on Power Electronics for Distributed Generation Systems.

[10]  T. Chow,et al.  A comparative evaluation of new silicon carbide diodes and state-of-the-art silicon diodes for power electronic applications , 1999, Conference Record of the 1999 IEEE Industry Applications Conference. Thirty-Forth IAS Annual Meeting (Cat. No.99CH36370).

[11]  Dushan Boroyevich,et al.  Voltage-balance limits in four-level diode-clamped converters with passive front ends , 2005, IEEE Transactions on Industrial Electronics.

[12]  Milan M. Jovanovic,et al.  Single-phase three-level boost power factor correction converter , 1995, Proceedings of 1995 IEEE Applied Power Electronics Conference and Exposition - APEC'95.

[13]  J.W. Kolar,et al.  Comparative evaluation of soft-switching concepts for bi-directional buck+boost dc-dc converters , 2010, The 2010 International Power Electronics Conference - ECCE ASIA -.

[14]  J.M. Ramirez,et al.  A novel two switches based DC-DC multilevel voltage multiplier , 2008, 2008 International Symposium on Power Electronics, Electrical Drives, Automation and Motion.

[15]  U. Drofenik,et al.  A General Scheme for Calculating Switching- and Conduction-Losses of Power Semiconductors in Numerical Circuit Simulations of Power Electronic Systems; International Power Electronics Conference; ; IPEC-Niigata 2005 , 2005 .

[16]  J.W. Kolar,et al.  Impact of Power Density Maximization on Efficiency of DC–DC Converter Systems , 2009, IEEE Transactions on Power Electronics.

[17]  J.M. Ramirez,et al.  Novel DC-DC Multilevel Boost Converter , 2008, 2008 IEEE Power Electronics Specialists Conference.