A 156 Mbps CMOS clock recovery circuit for burst-mode transmission
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This paper describes a new timing circuit design technique for asynchronous burst-mode data transmission, such as Fiber To The Home (FTTH). Without external reference clock signals, it enables the quick extraction of clock signal from received NRZ data packets using a "gating timing circuit" and "burst PLL". The circuit's simple configuration reduces both size and power. A fabricated 0.5-/spl mu/m CMOS IC exhibits instantaneous response within one bit for 156 Mbps asynchronous data packets.
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