A high speed multi-level-parallel array processor for vision chips

This paper proposes a high speed multi-level-parallel array processor for programmable vision chips. This processor includes 2-D pixel-parallel processing element (PE) array and 1-D row-parallel row processor (RP) array. The two arrays both operate in a single-instruction multiple-data (SIMD) fashion and share a common instruction decoder. The sizes of the arrays are scalable according to dedicated applications. In PE array, each PE can communicate not only with its nearest neighbor PEs, but also with the next near neighbor PEs in diagonal directions. This connection can help to speed up local operations in low-level image processing. On the other hand, global operations in mid-level processing are accelerated by the skipping chain and binary boosters in RP array. The array processor was implemented on an FPGA device, and was successfully tested for various algorithms, including real-time face detection based on PPED algorithm. The results show that the image processing speed of proposed processor is much higher than that of the state-of-the-arts digital vision chips.

[1]  Jun Ohta,et al.  Smart CMOS Image Sensors and Applications , 2007 .

[2]  David G. Lowe,et al.  Distinctive Image Features from Scale-Invariant Keypoints , 2004, International Journal of Computer Vision.

[3]  M. Ishikawa,et al.  A CMOS vision chip with SIMD processing element array for 1 ms image processing , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[4]  Bo Zhao,et al.  A 64$\,\times\,$64 CMOS Image Sensor With On-Chip Moving Object Detection and Localization , 2012, IEEE Transactions on Circuits and Systems for Video Technology.

[5]  Michael W. Hoffman,et al.  A CMOS Imager With Focal Plane Compression Using Predictive Coding , 2007, IEEE Journal of Solid-State Circuits.

[6]  陈凡,et al.  Institute of Microelectronics, Tsinghua University, Beijing 100084, China , 2013 .

[7]  Tadashi Shibata,et al.  An image representation algorithm compatible with neural-associative-processor-based hardware recognition systems , 2003, IEEE Trans. Neural Networks.

[8]  M. Ishikawa,et al.  A dynamically reconfigurable SIMD processor for a vision chip , 2003, IEEE Journal of Solid-State Circuits.

[9]  Zhihua Wang,et al.  A high-speed vision processor based on pixel-parallel PE array and its applications , 2010, 2010 IEEE Youth Conference on Information, Computing and Telecommunications.

[10]  Idaku Ishii,et al.  A digital vision chip specialized for high-speed target tracking , 2003 .

[11]  M. Ikeda,et al.  A 375 /spl times/ 365 high-speed 3-D range-finding image sensor using row-parallel search architecture and multisampling technique , 2005, IEEE Journal of Solid-State Circuits.

[12]  Piotr Dudek,et al.  A general-purpose processor-per-pixel analog SIMD vision chip , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Chih-Chi Cheng,et al.  iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor , 2009, IEEE Journal of Solid-State Circuits.

[14]  S. M. Steve.  SUSAN - a new approach to low level image processing , 1997 .

[15]  Ángel Rodríguez-Vázquez,et al.  ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Wancheng Zhang,et al.  A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors , 2009, Sensors.

[17]  Liang-Gee Chen,et al.  iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor , 2009, IEEE J. Solid State Circuits.

[18]  Gunhee Han,et al.  A 200 $\mu$ s Processing Time Smart Image Sensor for an Eye Tracker Using Pixel-Level Analog Image Processing , 2009, IEEE Journal of Solid-State Circuits.

[19]  Kiyoharu Aizawa,et al.  Computational Sensors - Vision VLSI , 1999 .

[20]  C.G. Sodini,et al.  A CMOS Imager With a Programmable Bit-Serial Column-Parallel SIMD/MIMD Processor , 2009, IEEE Transactions on Electron Devices.

[21]  Timothy K. Horiuchi.  A Low-Power Visual-Horizon Estimation Chip , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  Wancheng Zhang,et al.  A Programmable SIMD Vision Chip for Real-Time Vision Applications , 2008, IEEE Journal of Solid-State Circuits.

[23]  Jaehyuk Choi,et al.  A Spatial-Temporal Multiresolution CMOS Image Sensor With Adaptive Frame Rates for Tracking the Moving Objects in Region-of-Interest and Suppressing Motion Blur , 2007, IEEE Journal of Solid-State Circuits.

[24]  I. Ishii,et al.  Higher Order Autocorrelation Vision Chip , 2006, IEEE Transactions on Electron Devices.

[25]  Wancheng Zhang,et al.  A Programmable Vision Chip Based on Multiple Levels of Parallel Processors , 2011, IEEE Journal of Solid-State Circuits.

[26]  Gert Cauwenberghs,et al.  CMOS Camera With In-Pixel Temporal Change Detection and ADC , 2007, IEEE Journal of Solid-State Circuits.

[27]  Matthijs C. Dorst.  Distinctive Image Features from Scale-Invariant Keypoints , 2011 .

[28]  M. Paindavoine,et al.  A 10 000 fps CMOS Sensor With Massively Parallel Image Processing , 2008, IEEE Journal of Solid-State Circuits.

[29]  David Stoppa,et al.  A CMOS 3-D Imager Based on Single Photon Avalanche Diode , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[30]  Piotr Dudek,et al.  A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[31]  Jitendra Malik,et al.  Scale-Space and Edge Detection Using Anisotropic Diffusion , 1990, IEEE Trans. Pattern Anal. Mach. Intell..