Analog Integrated Circuit Sizing and Layout Dependent Effects: A Review

In order to generate a quality-guaranteed tape-out as the objective of CMOS design, diverse analog integrated circuit synthesis flows have been proposed to address the drawbacks of the traditional iterative design flow that may meet performance requirements but super time-consuming. Due to the indispensable impact of Layout Dependent Effects (LDEs) on electrical performance, standard models of LDEs have been developed to consider stress incurred effects such that simulation tools with built-in LDE models would provide results with higher accuracy at the advanced technology nodes. In addition to a survey of the universal synthesis flows, this paper put more emphasis on layout-aware circuit sizing by exhibiting a comprehensive literature review in this area. In particular, two dominant LDEs, Well Proximity Effects (WPE) and Shallow Trench Isolation (STI) effects, are discussed along with our experiments that aim to illustrate the severity of the induced performance degradation especially on sensitive devices even in the general analog integrated circuit building-blocks. Based on the exposed relationship between LDEs and circuit performance as per our experiments, the layout-related issues need to be seriously addressed in the next-generation analog synthesis methodologies and flows.

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