AN EXPERIMENTAL, single 5V 16Mb CMOS DRAM with a 3.3V internal operating voltage for a memory array, typical access time of 6011s and power dissipation of 420mW at a 180ns cycle time, will be reported. Among the design improvements are a transposed data-line structure for array noise suppression and a negative feedback preamplifier for the I/O lines for highspeed data transmission. Substantial data-line interference noise due t o an increase in inter-data line capacitance is predicted in scaled DRAM cell arrays described earlier’”. Furthermore, a new kind of data-line interference noise, generated during sense amplifier operation, has been observed. Experimental data indicate that these problems represent major limiting factors for 16Mb DRAMs. A proposed solution is a transposed data-line structure where a noise suppression by a factor of more than three has been achieved. Figure 1 illustrates a simplified model of the foregoing mechanism. For the sake of simplicity, only interference through inter-data-line capacitance, CM, between data-linesTO and n1 is a factor here. The differential noise, -61, is generated i n n o when the signal voltage, -Vs, appears in DI; -61, introduces the newly observed intereference noise, -62, during sense amplifier operation. Voltage amplification in data-line D1 starts earlier than that in D_o due to the difference in the refere_nce voltages, 61 in Do and D1. Since Do is in a floating state, Do receives the additional differential noise, -62, from D1 during the delay time ( t i t2) as shown in Figure l b . To overcome the noise problem, the transposed data-line structure shown in Figure IC is proposed. Here the differential noise is cancelled by converting it into the common mode noise, -61/2. Additionally, the smaller noise