A 223Mbps FPGA Implementation of (10240, 5120) Irregular Structured Low Density Parity Check Decoder

This paper presents a high speed decoder architecture for irregular structured low density parity check (LDPC) codes and its field programmable gate array (FPGA) implementation. Algorithm transformation and architectural level optimizations are employed to reduce the critical path. The enhanced semi-parallel architecture is easily scalable and reconfigurable for larger block sizes and can be well suited for achieving high decoding throughput. Based on the proposed architecture, a (10240, 5120) irregular structured LDPC decoder is implemented on Xilinx FPGA Virtex-4 VLX80, the FPGA implementation results show that the irregular LDPC decoder can achieve a maximum (information data) decoding throughput of 223 Mbps at 18 iterations.

[1]  Yanni Chen,et al.  A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder , 2003, GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489).

[2]  Keshab K. Parhi,et al.  A 54 Mbps (3,6)-regular FPGA LDPC decoder , 2002, IEEE Workshop on Signal Processing Systems.

[3]  A. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[4]  Joseph R. Cavallaro,et al.  Semi-parallel reconfigurable architectures for real-time LDPC decoding , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

[5]  Robert G. Gallager.  Low Density Parity Check Code , 1962 .

[6]  Tong Zhang,et al.  Joint (3,k)-regular LDPC code and decoder/encoder design , 2004, IEEE Transactions on Signal Processing.

[7]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[8]  A. J. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[9]  Zhongfeng Wang,et al.  A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA , 2006, 2006 IEEE International Symposium on Circuits and Systems.