Design and FPGA implementation of MAC using fault tolerant reversible logic gates

The Reversible logic gates implement the functions which are having one to one mapping between the input and output. Unlike irreversible logic circuits the information cannot be lost as the input vector can be recovered from the corresponding output vector. The dissipation of heat is also less in reversible logic gates. Therefore the reversible logic gates have immense number of applications in Low power CMOS design, quantum computing, Nano technology and digital signal processing. This paper proposes a novel 4×4 bit reversible fault tolerant MAC unit. The MAC unit Composed of a multiplier, adder and an accumulation unit. The Ripple Carry Adder and multiplier used in the proposed work were designed using parity preserving gates. The basic building blocks for adder and multiplier used were IG gate, Fredkin gate which are parity preserving gates. Therefore the proposed MAC unit has characteristic attribute of detecting any errors in output side. The synthesis and simulation was done by using Xilinx software and Model Sim Simulator.