Skew measurements in clock distribution circuits using an analytic signal method

This paper presents the application of a new analytic signal method for measuring several different kinds of clock skew in the clock distribution network of microprocessors. First, key terms are defined, and other existing skew measurement methods are reviewed. Then, detailed steps are given for applying the new method for measuring skew between a master and distributed clocks, between two distributed clocks, and between different frequency clocks that are related by frequency division. An indirect procedure for measuring deterministic clock skew is also proposed. Next, the new method is validated with experimental data from a prototype microprocessor test. Performance comparison is performed between the analytic signal method and the two-probe method. Finally, the measurement requirements of the proposed analytic signal method are compared with those of conventional methods.

[1]  Takahiro J. Yamaguchi,et al.  Testing clock distribution circuits using an analytic signal method , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[2]  Xiaohong Jiang,et al.  Statistical skew modeling for general clock distribution networks in presence of process variations , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Michael John Sebastian Smith,et al.  Application-specific integrated circuits , 1997 .

[4]  Takahiro J. Yamaguchi,et al.  A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[5]  Keith A. Jenkins,et al.  Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor , 1998, IEEE J. Solid State Circuits.

[6]  John G. Proakis,et al.  Probability, random variables and stochastic processes , 1985, IEEE Trans. Acoust. Speech Signal Process..

[7]  G. Gerosa,et al.  A wide-bandwidth low-voltage PLL for PowerPC microprocessors , 1995 .

[8]  H. Saunders,et al.  Probability, Random Variables and Stochastic Processes (2nd Edition) , 1989 .

[9]  Michael Snyder,et al.  A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect , 1999 .

[10]  Takahiro J. Yamaguchi,et al.  Jitter measurements of a PowerPC/sup TM/ microprocessor using an analytic signal method , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[11]  Baris Taskin,et al.  Timing Optimization Through Clock Skew Scheduling , 2000 .

[12]  H. Fair,et al.  Clocking design and analysis for a 600 MHz Alpha microprocessor , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[13]  Leendert M. Huisman,et al.  Diagnosis and characterization of timing-related defects by time-dependent light emission , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[14]  Tadahiro Ohmi,et al.  Extraction of peak-to-peak and RMS sinusoidal jitter using an analytic signal method , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[15]  Mani Soma,et al.  Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method , 2003 .

[16]  David Harris,et al.  Skew-Tolerant Circuit Design , 2000 .

[17]  Steven Kasapi,et al.  Practical, non-invasive optical probing for flip-chip devices , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[18]  S. Naffziger,et al.  Statistical clock skew modeling with data delay variations , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[19]  K.A. Jenkins,et al.  The clock distribution of the Power4 microprocessor , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[20]  K.A. Jenkins,et al.  A clock distribution network for microprocessors , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).